AD7655ASTZ Analog Devices Inc, AD7655ASTZ Datasheet - Page 5

• Manufacturer Part Number: AD7655ASTZ
• Description: IC ADC 16BIT 1MSPS QUAD 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7655ASTZ

• Data Interface: Serial, Parallel
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 135mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 16bit
• Sampling Rate: 1MSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Package: 48LQFP
• Resolution: 16 Bit
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 4
• Digital Interface Type: Parallel|Serial (2-Wire, SPI, QSPI, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 86(Typ) dB
• Polarity Of Input Voltage: Unipolar
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7655CBZ - BOARD EVALUATION FOR AD7655
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; V
Table 3.
Parameter
CONVERSION AND RESET (See Figure 21 and Figure 22)
PARALLEL INTERFACE MODES (See Figure 23 to Figure 27)
MASTER SERIAL INTERFACE MODES (See Figure 28 and Figure 29)
Convert Pulse Width
Time Between Conversions
CNVST Low to BUSY High Delay
BUSY High All Modes Except in Master Serial Read After Convert Mode
Aperture Delay
End of Conversions to BUSY Low Delay
Conversion Time
Acquisition Time
RESET Pulse Width
CNVST Low to EOC High Delay
EOC High for Channel A Conversion
EOC Low after Channel A Conversion
EOC High for Channel B Conversion
Channel Selection Setup Time
Channel Selection Hold Time
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
A/B Low to Data Valid Delay
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
SYNC Asserted to SCLK First Edge Delay
Internal SCK Period
Internal SCLK High
Internal SCLK Low
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read after Convert
CNVST Low to SYNC Asserted Delay
SYNC Deasserted to BUSY Low Delay
(Normal Mode/Impulse Mode)
(Normal Mode/Impulse Mode)
(Normal Mode/Impulse Mode)
(Normal Mode/Impulse Mode)
(Normal Mode/Impulse Mode)
(Normal Mode/Impulse Mode)
2
2
2
2
2
2
1
2
REF
= 2.5 V; all specifications T
Rev. B | Page 5 of 28
MIN
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
to T
MAX
, unless otherwise noted.
Min
5
2/2.25
10
250
10
45
250
14
5
3
23
12
7
4
2
1
Typ
2
250/500
See Table 4
0.75/1
25
Max
32
1.75/2
1.75/2
30
1/1.25
0.75
30
1.75/2
40
15
40
10
10
10
40
10
10
10
AD7655
Unit
ns
μs
ns
μs
ns
ns
μs
ns
ns
ns
μs
ns
μs
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns