AD7655ASTZ Analog Devices Inc, AD7655ASTZ Datasheet - Page 6

IC ADC 16BIT 1MSPS QUAD 48-LQFP

AD7655ASTZ

Manufacturer Part Number
AD7655ASTZ
Description
IC ADC 16BIT 1MSPS QUAD 48-LQFP
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet

Specifications of AD7655ASTZ

Data Interface
Serial, Parallel
Number Of Bits
16
Sampling Rate (per Second)
1M
Number Of Converters
1
Power Dissipation (max)
135mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
16bit
Sampling Rate
1MSPS
Input Channel Type
Single Ended
Supply Voltage Range - Analog
4.75V To 5.25V
Package
48LQFP
Resolution
16 Bit
Architecture
SAR
Number Of Adcs
1
Number Of Analog Inputs
4
Digital Interface Type
Parallel|Serial (2-Wire, SPI, QSPI, Microwire)
Input Type
Voltage
Signal To Noise Ratio
86(Typ) dB
Polarity Of Input Voltage
Unipolar
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7655CBZ - BOARD EVALUATION FOR AD7655
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7655ASTZ
Manufacturer:
ADI
Quantity:
2
Part Number:
AD7655ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7655ASTZ
Manufacturer:
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Part Number:
AD7655ASTZRL
Manufacturer:
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Quantity:
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AD7655
Parameter
SLAVE SERIAL INTERFACE MODES (See Figure 31 and Figure 32)
1
2
Table 4. Serial Clock Timings in Master Read After Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Typical
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
Symbol
t
t
t
t
t
t
t
t
t
t
25
26
26
27
28
29
30
31
35
35
Rev. B | Page 6 of 28
0
0
3
25
40
12
7
4
2
1
3.25
3.5
L
Symbol
t
t
t
t
t
t
t
of 10 pF; otherwise C
38
39
40
41
42
43
44
0
1
17
50
70
22
21
18
4
3
4.25
4.5
Min
5
3
5
5
25
10
10
1
0
17
100
140
50
49
18
30
30
6.25
6.5
L
is 60 pF maximum.
Typ
1
1
17
200
280
100
99
18
80
80
10.75
11
Max
18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
Unit
ns
ns
ns
ns
ns
ns
ns

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