ADC0838CCN/NOPB National Semiconductor, ADC0838CCN/NOPB Datasheet - Page 15

IC ADC 8BIT SERIAL I/O 20-DIP

ADC0838CCN/NOPB

Manufacturer Part Number
ADC0838CCN/NOPB
Description
IC ADC 8BIT SERIAL I/O 20-DIP
Manufacturer
National Semiconductor
Datasheet

Specifications of ADC0838CCN/NOPB

Number Of Bits
8
Sampling Rate (per Second)
31k
Data Interface
NSC MICROWIRE™, Serial
Number Of Converters
1
Power Dissipation (max)
15mW
Voltage Supply Source
Single Supply
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*ADC0838CCN
*ADC0838CCN/NOPB
ADC0838
ADC0838CCN
Functional Description
Since the input configuration is under software control, it can
be modified, as required, at each conversion. A channel can
be treated as a single-ended, ground referenced input for
one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illus-
trates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above V
without degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system
improvements; it allows more function to be included in the
(Continued)
CC
TABLE 6. MUX Addressing: ADC0832
TABLE 7. MUX Addressing: ADC0832
COM is internally tied to A GND
Single-Ended MUX Mode
Differential MUX Mode
MUX Address
SGL/
MUX Address
SGL/
(typically 5V)
DIF
DIF
1
1
0
0
ODD/
ODD/
SIGN
SIGN
0
1
0
1
15
0
+
0
+
Channel #
Channel #
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmitting
highly noise immune digital data back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate diagram is shown of each device.
1. A conversion is initiated by first pulling the CS (chip select)
line low. This line must be held low for the entire conversion.
The converter is now waiting for a start bit and its MUX
assignment word.
2. A clock is then generated by the processor (if not provided
continuously) and output to the A/D clock input.
+
+
1
1
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