MAX148BCAP+ Maxim Integrated Products, MAX148BCAP+ Datasheet - Page 14

• Manufacturer Part Number: MAX148BCAP+
• Description: IC ADC SRL 8CH 10BIT LP 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX148BCAP+

• Number Of Bits: 10
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 640mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Table 4. Typical Power-Up Delay Times
the control byte (the PD0 bit) is clocked into DIN. The
start bit is defined as follows:
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized
as a start bit; the current conversion is terminated, and
a new one is started.
The fastest the MAX148/MAX149 can run with CS held
low between conversions is 15 clocks per conversion.
Figure 11a shows the serial-interface timing necessary
to perform a conversion every 15 SCLK cycles in exter-
nal clock mode. If CS is tied low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers (FCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a FC can drive the
MAX148/MAX149. Figure 11b shows the serialinterface
timing necessary to perform a conversion every 16 SCLK
cycles in external clock mode.
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX148/MAX149 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies stabi-
lize, the internal reset time is 10Fs, and no conversions
should be performed during this phase. SSTRB is high
on power-up and, if CS is low, the first logical 1 on DIN is
interpreted as a start bit. Until a conversion takes place,
DOUT shifts out zeros. Also see Table 4.
14
The first high bit clocked into DIN with CS low any time
the converter is idle; e.g., after V
The first high bit clocked into DIN after bit 3 of a con-
version in progress is clocked onto the DOUT pin.
REFERENCE
_____________________________________________________________________________________
BUFFER
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Applications Information
COMPENSATION
REFERENCE-
BUFFER
External
External
Internal
Internal
MODE
OR
—
—
DD
Power-On Reset
is applied.
CAPACITOR
VREF
(µF)
4.7
4.7
—
—
—
—
POWER-DOWN
In addition to its shutdown function, SHDN selects inter-
nal or external compensation. The compensation affects
both power-up time and maximum conversion speed.
The 100kHz minimum clock rate is limited by droop on
the sample-and-hold and is independent of the compen-
sation used.
Unconnect SHDN to select external compensation. The
Typical Operating Circuit uses a 4.7FF capacitor at VREF.
A 4.7FF value ensures reference-buffer stability and
allows converter operation at the 2MHz full clock speed.
External compensation increases power-up time (see the
Choosing Power-Down Mode section and Table 4).
Pull SHDN high to select internal compensation. Internal
compensation requires no external capacitor at VREF
and allows for the shortest power-up times. The maxi-
mum clock rate is 2MHz in internal clock mode and
400kHz in external clock mode.
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down mode or fast power-down mode via bits 1
and 0 of the DIN control byte with SHDN high or uncon-
nected (Tables 1 and 5). In both software power-down
modes, the serial interface remains operational, but the
ADC does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current to
2FA (typ). Fast power-down mode turns off all circuitry
except the bandgap reference. With fast power-down
mode, the supply current is 30FA. Power-up time can be
shortened to 5Fs in internal compensation mode.
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
MODE
Fast
Fast
Fast
Full
Full
Full
POWER-UP DELAY
See Figure 14c
See Figure 14c
Choosing Power-Down Mode
Reference-Buffer Compensation
(µs)
300
5
2
2
SAMPLING RATE
MAXIMUM
(ksps)
133
133
133
133
26
26