MAX148BCAP+ Maxim Integrated Products, MAX148BCAP+ Datasheet - Page 15

• Manufacturer Part Number: MAX148BCAP+
• Description: IC ADC SRL 8CH 10BIT LP 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX148BCAP+

• Number Of Bits: 10
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 640mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Voltage
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7FF com-
pensation capacitor when the capacitor is initially fully
discharged. From fast power-down, startup time can be
eliminated by using low-leakage capacitors that do not
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Figure 12a. Timing Diagram Power-Down Modes, External Clock
DOUT
SCLK
DIN
CLOCK
CS
MODE
MODE
SHDN
DOUT
SSTRB
DOUT
SCLK
DIN
DIN
CS
S X X X X X 1 1
S
1
S
1
______________________________________________________________________________________
CONTROL BYTE 0
+2.7V to +5.25V, Low-Power, 8-Channel,
CONTROL BYTE 0
SETS EXTERNAL
CLOCK MODE
10 + 2 DATA BITS
POWERED UP
8
8
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
B9
S
B8
X
X
B7
X
CONVERSION RESULT 0
X
B6
X
EXTERNAL
CONVERSION RESULT 0
0 0
15
B5
S
SETS SOFTWARE
POWER-DOWN
1
B4
16
B3
10 + 2 DATA BITS
discharge more than ½ LSB while shut down. In power-
down, leakage currents at VREF cause droop on the
reference bypass capacitor. Figures 12a and 12b show
the various power-down sequences in both external and
internal clock modes.
CONTROL BYTE 1
B2
S
1
B1
B0
CONTROL BYTE 1
POWER-DOWN
S1
SOFTWARE
Serial 10-Bit ADCs
S0
SETS EXTERNAL
8
CLOCK MODE
S
X X X X X
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
POWERED UP
8
1 1
CONVERSION RESULT 1
VALID
DATA
POWER-DOWN
15
HARDWARE
EXTERNAL
B9
CONVERSION RESULT 1
INVALID
DATA
S
1
B8
B7
CONTROL BYTE 2
B6
POWERED UP
16
15