MAX145ACUA+ Maxim Integrated Products, MAX145ACUA+ Datasheet - Page 7

• Manufacturer Part Number: MAX145ACUA+
• Description: IC ADC 12BIT 108KSPS 8-UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX145ACUA+

• Number Of Bits: 12
• Sampling Rate (per Second): 108k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 330mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX144/MAX145 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track-and-hold (T/H)
structure to convert an analog signal to a serial 12-bit
digital output data stream.
This flexible serial interface provides easy interface to
microprocessors (µPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX144 (2 channels, single-ended) and the MAX145
(1 channel, pseudo-differential).
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit of
Figure 3. In single-ended mode (MAX144), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted and
the conversions will continue to alternate between
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however, the output
data will still contain the channel identification bit
(before the MSB).
For the MAX145, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ±0.5LSB (±0.1LSB for optimum results) with
respect to GND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
Figure 1. Load Circuits for Enable and Disable Time
_______________Detailed Description
Analog Inputs: Single-Ended (MAX144)
and Pseudo-Differential (MAX145)
a) HIGH-Z TO V
DOUT
_______________________________________________________________________________________
+2.7V, Low-Power, 2-Channel, 108ksps,
6k
0H
, V
0L
TO V
GND
0H
, AND V
Serial 12-Bit ADCs in 8-Pin µMAX
C
OH
L
TO HIGH-Z
HOLD
. The
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on C
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
Figure 2. Simplified Functional Diagram
Figure 3. Analog Input Channel Structure
CS/SHDN
SCLK
(CH+)
(CH-)
REF
CH0
CH1
SINGLE-ENDED MODE: CH0, CH1 = IN+; GND = IN-
DIFFERENTIAL-ENDED MODE: CH+ = IN+; CH- = IN-
GND
(CH+)
CH1
(CH-)
REF
CH0
(2 CHANNEL)
b) HIGH-Z TO V
ANALOG
INPUT
MUX
DOUT
HOLD
INPUT
C
MUX
HOLD
SWITCH
0L
CONTROL
12-BIT CAPACITIVE DAC
, V
LOGIC
from the positive input (IN+) to the
T/H
0H
6k
as a sample of the signal at IN+.
TO V
C
16pF
HOLD
TRACK
0L
V
9k
C
IN
DD
R
, AND V
GND
L
IN
INTERNAL
12-BIT
SCLK
CLOCK
ADC
SAR
OL
TO HIGH-Z
OUT
ZERO
T/H
( ) ARE FOR MAX145
CONTROL LOGIC
HOLD
( ) ARE FOR MAX145
REGISTER
COMPARATOR
OUTPUT
MAX144
MAX145
MAX144
MAX145
TO SAR
DOUT
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