LTC2418CGN#TR Linear Technology, LTC2418CGN#TR Datasheet
LTC2418CGN#TR
Specifications of LTC2418CGN#TR
Available stocks
Related parts for LTC2418CGN#TR
LTC2418CGN#TR Summary of contents
Page 1
... The LTC2414/LTC2418 communicate through a flexible 4-wire digital interface that is compatible with SPI and MICROWIRE , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. 2.7V TO 5.5V 1µF ...
Page 2
LTC2414/LTC2418 ABSOLUTE AXI U RATI GS Supply Voltage ( GND .......................– 0. Analog Input Voltage to GND ....... – 0. Reference Input Voltage to GND .. – 0. ...
Page 3
ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T PARAMETER CONDITIONS 0.1V ≤ V Resolution (No Missing Codes) REF 4.5V ≤ V Integral Nonlinearity CC 5V ≤ V ≤ 5.5V, REF CC + REF = 2.5V, REF 2.5V ≤ REF ...
Page 4
LTC2414/LTC2418 ALOG I PUT A D REFERE CE temperature range, otherwise specifications are at T SYMBOL PARAMETER + IN Absolute/Common Mode IN – IN Absolute/Common Mode IN V Input Differential Voltage Range IN + – (IN ...
Page 5
U U DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V Low Level Output Voltage OL SDO V High Level Output Voltage OH SCK V Low Level Output Voltage OL SCK ...
Page 6
LTC2414/LTC2418 CHARACTERISTICS range, otherwise specifications are SYMBOL PARAMETER CS ↓ to SDO Low ↑ to SDO High ↓ to SCK ↓ ↓ to SCK ...
Page 7
W U TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error ( 5V) CC REF GND REF 2.5V INCM REFCM 1 ...
Page 8
LTC2414/LTC2418 W U TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs Input Differential Voltage 0 GND 25° 0 REF V = 2.5V INCM 0.3 0.2 0.1 0 ...
Page 9
W U TYPICAL PERFOR A CE CHARACTERISTICS Full-Scale Error vs Temperature GND REF 2.5V INCM 2 +FS ERROR 1 0 –1 –2 –FS ERROR –3 ...
Page 10
LTC2414/LTC2418 CTIO S CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8): Analog Inputs. May be programmed for single-ended or differen- tial mode. CH8 to CH15 (Pin 1 to Pin ...
Page 11
CTIO AL BLOCK DIAGRA V CC GND + REF – REF CH0 CH1 • • MUX • CH15 COM TEST CIRCUITS SDO 1.69k 241418 TA02 Hi Hi-Z ...
Page 12
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO POWER UP + – CH0 CH1 CONVERT SLEEP FALSE CS = LOW AND SCK TRUE DATA OUTPUT ADDRESS INPUT 241418 F02 Figure 2. LTC2414/LTC2418 State Transition Diagram first ...
Page 13
U U APPLICATIO S I FOR ATIO + – specification for the REF and REF range from GND For correct converter operation the REF pin must always be more positive than the REF pin. The ...
Page 14
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO CS BIT31 BIT30 BIT29 BIT28 SDO EOC DMY SIG MSB Hi-Z SCK SDI SGL SLEEP CONVERSION RESULT N – 1 SDO ADDRESS N – 1 SCK SDI ADDRESS N ...
Page 15
U U APPLICATIO S I FOR ATIO Table 2. Channel Selection for the LTC2418 MUX ADDRESS ODD/ SGL SIGN – ...
Page 16
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO parity bit representing the parity of the previous 31 bits. The parity bit is useful to check the output data integrity espe- cially when the output data is transmitted over a distance. ...
Page 17
U U APPLICATIO S I FOR ATIO Table 4. LTC2414/LTC2418 Output Data Format Differential Input Voltage ≥ 0.5 • REF 0.5 • – 1LSB REF 0.25 • REF ...
Page 18
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO Table 5. LTC2414/LTC2418 State Duration State Operating Mode CONVERT Internal Oscillator External Oscillator SLEEP DATA OUTPUT Internal Serial Clock External Serial Clock with Frequency f kHz SCK Serial Clock Input/Output (SCK) The ...
Page 19
U U APPLICATIO S I FOR ATIO last input bit A0 of SDI by the time CS pulled HIGH, the address information is discarded and the previous address is kept. Finally, CS can be used to control the free-running modes ...
Page 20
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. ...
Page 21
U U APPLICATIO S I FOR ATIO External Serial Clock, 3-Wire I/O This timing mode utilizes a 3-wire serial I/O interface. The conversion result is shifted out of the device by an exter- nally generated serial clock (SCK) signal, see ...
Page 22
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO TEST EOC <t EOCtest CS BIT 31 BIT 30 SDO EOC Hi-Z Hi-Z SCK (INTERNAL) SDI DON’T CARE (1) CONVERSION SLEEP SLEEP When testing EOC, if the conversion is complete (EOC = ...
Page 23
U U APPLICATIO S I FOR ATIO TEST EOC (OPTIONAL) > t EOCtest CS TEST EOC BIT 0 SDO EOC Hi-Z Hi-Z Hi-Z Hi-Z SCK (INTERNAL) SDI DON’T CARE SLEEP CONVERSION DATA OUTPUT SLEEP SLEEP Figure 9. Internal Serial Clock, ...
Page 24
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO CS BIT 31 BIT 30 SDO EOC SCK (INTERNAL) SDI DON’T CARE (1) (0) CONVERSION Figure 10. Internal Serial Clock Continuous Operation complete, SCK and SDO go LOW (EOC ...
Page 25
U U APPLICATIO S I FOR ATIO operation recommended to drive all digital input signals to full CMOS levels [V V > (V – 0.4V)]. OH CC During the conversion period, the undershoot and/or overshoot of a fast ...
Page 26
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO Input Current If complete settling occurs on the input, conversion re- sults will be unaffected by the dynamic input current. An incomplete settling of the input signal sampling process may result in ...
Page 27
U U APPLICATIO S I FOR ATIO 0.01µ 0.001µ 100pF 0pF REF = 5V – REF = GND + ...
Page 28
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO 300 1µF, 10µ REF = 5V – 240 REF = GND + IN = 3.75V – 1.25V F = GND 180 O ...
Page 29
U U APPLICATIO S I FOR ATIO values for C will deteriorate the converter offset and REF gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (C be ...
Page 30
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO In addition to this gain error, the converter INL perfor- mance is degraded by the reference source impedance. When F = LOW (internal oscillator and 60Hz notch), every O 100Ω of source ...
Page 31
U U APPLICATIO S I FOR ATIO mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching ...
Page 32
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO 25° 85° REF = 5V 17 – REF = GND 2.5V ...
Page 33
U U APPLICATIO S I FOR ATIO When external amplifiers are driving the LTC2414/ LTC2418, the ADC input referred system noise calculation can be simplified by Figure 32. The noise of an amplifier driving the LTC2414/LTC2418 input pin can be ...
Page 34
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO The combined normal mode rejection performance is shown in Figure 33 for the internal oscillator with 50Hz notch setting (F = HIGH) and in Figure 34 for the internal O oscillator with ...
Page 35
U U APPLICATIO S I FOR ATIO Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The pro- prietary architecture used for the LTC2414/LTC2418 third order modulator resolves ...
Page 36
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO BRIDGE APPLICATIONS Typical strain gauge based bridges deliver only 2mV/Volt of excitation. As the maximum reference voltage of the LTC2414/LTC2418 is 5V, remote sensing of applied exci- tation without additional circuitry requires ...
Page 37
U U APPLICATIO S I FOR ATIO The circuit in Figure 42 shows an example of a simple amplification scheme. This example produces a differen- tial output with a common mode voltage of 2.5V, as determined by the bridge. The ...
Page 38
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO Figure 43 shows an example of a single amplifier used to produce single-ended gain. This topology is best used in applications where the gain setting resistor can be made to match the ...
Page 39
U U APPLICATIO S I FOR ATIO The basic circuit shown in Figure 44 shows connections for a full 4-wire connection to the sensor, which may be located remotely. The differential input connections will reject induced or coupled 60Hz interference, ...
Page 40
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO The error associated with the 10V excitation would be –80ppm. Hence, overall reference error could be as high as 130ppm, the average of the two. Figure 47 shows a similar scheme to ...
Page 41
U U APPLICATIO S I FOR ATIO Q1 2N3904 22Ω 10V 350Ω BRIDGE TWO ELEMENTS VARYING 33Ω ×2 Q2, Q3 2N3906 ×2 Figure 47. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier MULTIPLE CHANNEL USAGE The LTC2414/LTC2418 have ...
Page 42
... LabVIEW which graphically captures the conversion results. It can be used to determine noise performance, stability and with an external source linearity. As exemplified in the sche- matic, the LTC2414/LTC2418 is extremely easy to use. This demonstration board and associated software is available by contacting Linear Technology. PIC16F84 18 8 RB2 SCK ...
Page 43
U U APPLICATIO S I FOR ATIO // LTC2418 PIC16F84 Interface Example // Written for CC5X Compiler // Processor is PIC16F84 running at 10 MHz #include <16f84.h> #include <int16cxx.h> #pragma origin = 0x4 #pragma config |= 0x3fff, WDTE=off,FOSC=HS // global ...
Page 44
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO ////////// Bidirectional Shift Routine for ADC ////////// void shiftbidir(char nextch) { int i; for(i=0;i<2;i++) { sdi=nextch.7; nextch = rl(nextch); sck=1; sck=0; } for(i=0;i<8;i++) { sdi=nextch.7; nextch = rl(nextch); result_3 = rl(result_3);// get ...
Page 45
U U APPLICATIO S I FOR ATIO JP1 V JMPR CC LT1460ACN8-2 OUT + 2 C1 10µF 35V R2 3Ω BANANA 2.5V 5V JACK 1 3 JP3 J1 JMPR 2 VEX ...
Page 46
LTC2414/LTC2418 U U APPLICATIO S I FOR ATIO Top Silkscreen Figure 52. LTC2418 Demo Program Display Top Layer Figure 53. PCB Layout and Film Bottom Layer 241418fa ...
Page 47
... FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...
Page 48
... REF LTC2418 21 CH0 20 22 CH1 SDI 18 23 CH2 SCK 17 24 CH3 SDO • • • • • • CH14 CH15 COM GND GND 15 2418 F54 Noise P-P Noise RMS LT 1105 REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2005 241418fa ...