AD1377KD Analog Devices Inc, AD1377KD Datasheet - Page 6

• Manufacturer Part Number: AD1377KD
• Description: IC ADC SNGL 16BIT 32-CDIP
• Manufacturer: Analog Devices Inc

Specifications of AD1377KD

• Data Interface: Parallel
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 111k
• Number Of Converters: 1
• Power Dissipation (max): 800mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (0.900", 22.86)
• Resolution (bits): 16bit
• Sampling Rate: 100kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Digital: 4.75V To 5.25V
• Supply Current: -23mA
• Digital Ic Case Style: DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD1376/AD1377
DESCRIPTION OF OPERATION
On receipt of a CONVERT START command, the AD1376/
AD1377 convert the voltage at the analog input into an
equivalent 16-bit binary number. This conversion is
accomplished as follows: the 16-bit successive approximation
register (SAR) has its 16-bit outputs connected both to the
device bit output pins and to the corresponding bit inputs of the
–0.0030
–0.0060
–0.0080
–0.0135
0.0135
0.0080
0.0060
0.0030
–0.038
–0.100
0.100
0.038
0.100
0.010
0.006
0.003
0.001
0
0
0
0
AD1376/AD1377KD
5
Figure 3. AD1376 Nonlinearity vs. Conversion Time
±0.003%, @ 25°C
±2ppm/°C,
10
Figure 4. Gain Drift Error vs. Temperature
Figure 2. Linearity Error vs. Temperature
20
TEMPERATURE (°C)
25
CONVERSION TIME (µs)
10
30
AD1376/AD1377JD
SHORT CYCLED TO 12 BITS
SHORT CYCLED TO 13 BITS
SHORT CYCLED TO 14 BITS
±0.006%, @ 25°C
AD1376
±3ppm/°C,
40
50
15
1/2LSB 12-BIT
1/2LSB 13-BIT
1/2LSB 14-BIT
60
70
70
0.0195
0.0120
0
–0.0120
–0.0195
0.068
0
–0.068
2
0
Rev. D | Page 6 of 12
feedback DAC. The analog input is successively compared to
the feedback DAC output, one hit at a time (MSB first, LSB
last). The decision to keep or reject each bit is then made at the
completion of each bit comparison period, depending on the
state of the comparator at that time.
GAIN ADJUSTMENT
The gain adjustment circuit consists of a 100 ppm/°C poten-
tiometer connected across ±V
through a 300 kΩ resistor to Pin 29 (GAIN ADJ) as shown in
Figure 5.
If no external trim adjustment is desired, Pin 27
(COMPARATOR IN) and Pin 29 can be left open.
ZERO OFFSET ADJUSTMENT
The zero offset adjustment circuit consists of a 100 ppm/°C
potentiometer connected across ±V
through a 1.8 MΩ resistor to Pin 27 for all ranges. As shown in
Figure 6, the tolerance of this fixed resistor is not critical; a carbon
composition type is generally adequate. Using a carbon compo-
sition resistor having a −1200 ppm/°C temperature coefficient
contributes a worst-case offset temperature coefficient of 32 LSB
× 61 ppm/LSB
adjustment potentiometer is set at either end of its adjustment
range. Since the maximum offset adjustment required is typically
no more than ±16 LSB
summing resistor typically contributes no more than 1 ppm/°C of
FSR offset temperature coefficient.
An alternate offset adjustment circuit, which contributes a
negligible offset temperature coefficient if metal film resistors
(temperature coefficient <100 ppm/°C) are used, is shown in
Figure 7.
OFFSET
ADJ
Figure 7. Low Temperature Coefficient Zero Adjustment Circuit
100ppm/°C
Figure 6. Zero Offset Adjustment Circuit (±0.3% FSR)
100kΩ
100kΩ
10kΩ
10kΩ
Figure 5. Gain Adjustment Circuit (±0.2% FSR)
TO
TO
14
+15V
–15V
+15V
–15V
100kΩ
× 1200 ppm/°C = 2.3 ppm/°C of FSR, if the offset
10kΩ
180kΩ M.F. 180kΩ M.F.
TO
+15V
–15V
1.8MΩ
14
, use of a carbon composition offset
300kΩ
0.01µF
22kΩ M.F.
27
S
with its slider connected
AD1376/AD1377
29
S
with its slider connected
AD1376/AD1377
27
AD1376/AD1377
14