MAX1414CAI+ Maxim Integrated Products, MAX1414CAI+ Datasheet - Page 28

• Manufacturer Part Number: MAX1414CAI+
• Description: IC DAS 16BIT LP 28-SSOP
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX1414CAI+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 60
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Number Of Converters: 1
• Resolution: 16 bit
• Interface Type: Serial (4-Wire, SPI, QSPI, Microwire)
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 762 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Writing to the DAC1 register will update the DAC1 output
(OUT1). The output voltage in a unity gain configuration is
V
Writing to the DAC2 register will update the DAC2 output
(OUT2). The output voltage in a unity-gain configuration is
V
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
The Offset register contains the 16-bit result from the
most recently completed ADC offset calibration. The
data format is two’s complement and is subtracted from
the filter output before writing to the Data register. After
power-up, the Offset register contains all zeros.
Each change in ambient operating condition (power
supply and temperature), PGA gain, bipolar/unipolar
input range, buffered/unbuffered mode, or conversion
speed requires an offset calibration. The offset for a
given ADC configuration can be read and stored by the
µP to avoid ADC recalibration. When returning to an
ADC configuration where the offset was stored, write
back the stored offset to the Offset register. The stored
offset stays valid as long as the ambient operating con-
dition remains unchanged (within ±20°C).
28
REF
REF
FIRST BIT (MSB)
FIRST BIT (MSB)
FIRST BIT (MSB)
DAC1[9]
DAC1[1]
DAC2[9]
DAC2[1]
OFF15
______________________________________________________________________________________
OFF7
x N/(2
x N/(2
10
10
), where N is the integer value of DAC1[9:0]
), where N is the integer value of DAC2[9:0]
DAC1[8]
DAC1[0]
DAC2[8]
DAC2[0]
OFF14
OFF6
DAC1[7]
DAC2[7]
OFF13
OFF5
x
x
DAC1[6]
DAC2[6]
OFF12
OFF4
x
x
(0 to 1023), and V
DAC. The DAC1 data is 10-bit long and left justified. After
power-up, the DAC1 register contains all zeros.
(0 to 1023), and V
DAC. The DAC2 data is 10-bit long and left justified. After
power-up, the DAC2 register contains all zeros.
Writing to the DAC1 register updates the output of
DAC1. Writing to the DAC2 register updates the output
of DAC2. The DAC data is 10-bit long and left justified.
Follow the timing diagrams of Figure 11 and Figure 13
to program these registers. Writing a logic 0 to the
DA1E or DA2E bit in the POWER2 register disables
DAC1 or DAC2, respectively. At power-up, DAC1 and
DAC2 are disabled.
DAC1[5]
DAC2[5]
OFF11
OFF3
x
x
DAC1[4]
DAC2[4]
OFF10
OFF2
(MAX1407/MAX1409/MAX1414 only)
x
x
REF
REF
is the reference voltage for the
is the reference voltage for the
Force Sense DAC Registers
OFFSET REGISTER (00011)
DAC1 REGISTER (00100)
DAC2 REGISTER (00101)
DAC1[3]
DAC2[3]
OFF9
OFF1
x
x
DAC1[2]
DAC2[2]
(LSB)
(LSB)
(LSB)
OFF8
OFF0
x
x