AD5292BRUZ-20 Analog Devices Inc, AD5292BRUZ-20 Datasheet - Page 25

• Manufacturer Part Number: AD5292BRUZ-20
• Description: IC POT DIG 1024P SPI 20K 14TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5292BRUZ-20

• Memory Type: Non-Volatile
• Temperature Coefficient: 35 ppm/°C Typical
• Design Resources: 30 V Low Cost DAC Using AD5292 Digital Potentiometer (CN0111) Variable Gain Noninverting Amplifier Using AD5292 and OP184 (CN0112) Variable Gain Inverting Amplifier Using AD5292 and OP184 (CN0113) Low Cost, High Voltage, Programmable Gain Instrumentation Amplifier Using AD5292 and AD8221 (CN0114) Programmable High Voltage Source with Boosted Output Current Using AD5292, OP184, and MOSFETs (CN0115) Programmable Bidirectional Current Source Using AD5292 and ADA4091-4 (CN0117) Logarithmic Audio Volume Control with Glitch Reduction Using AD5292 (CN0120)
• Taps: 1024
• Resistance (ohms): 20K
• Number Of Circuits: 1
• Interface: SPI Serial
• Voltage - Supply: 9 V ~ 33 V, ±9 V ~ 16.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 20K
• End To End Resistance: 20kohm
• Resistance Tolerance: ± 1%
• No. Of Steps: 1024
• Control Interface: Serial, SPI
• No. Of Pots: Single
• Supply Voltage Range: ± 9V To ± 16.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD5292BRUZ-20-U1; AD5292BRUZ-20-U1

RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor
tolerance that ensures a ±1% resistor tolerance on each code,
that is, code = half scale, R
(AD5291) or Table 5 (AD5292) to check which codes achieve
±1% resistor tolerance. The resistor performance mode is
activated by programming Bit C2 of the control register (see
Table 13 and Table 14). The typical settling time is shown in
Figure 50.
RESET
A low-to-high transition of the hardware RESET pin loads the
RDAC register with the contents of the most recently programmed
20-TP memory location. The AD5291 and AD5292 can also be
reset through software by executing Command 4 (see
If no 20-TP memory location is programmed, then the RDAC
register loads with midscale upon reset. The control register is
restored with default bits; see
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting, 50-TP values and
control register using Command 2, Command 5 and Command 7,
respectively (see Table 11) or the SDO pin can be used in daisy-
chain mode. Data is clocked out of SDO on the rising edge of
SCLK. The SDO pin contains an open-drain N-channel FET
that requires a pull-up resistor if this pin is used. To place the
pin in high impedance and minimize the power dissipation
when the pin is used, the 0x8001 data word followed by
Command 0 should be sent to the part. Table 17 provides a
sample listing for the sequence of the serial data input (DIN).
Daisy chaining minimizes the number of port pins required
from the controlling IC. As shown in Figure 64, users need to
tie the SDO pin of one package to the DIN pin of the next
package. Users may need to increase the clock period, because
the pull-up resistor and the capacitive loading at the SDO-to-
DIN interface may require additional time delay between
subsequent devices.
When two AD5291 and AD5292 devices are daisy-chained, 32
bits of data are required. The first 16 bits go to U2, and the
second 16 bits go to U1. Hold the SYNC pin low until all 32 bits
are clocked into their respective shift registers. The SYNC pin is
then pulled high to complete the operation.
Table 17. Minimize Power Dissipation at SDO Pin
DIN
0xXXXX
0x8001
0x0000
1
X is don’t care.
SDO
0xXXXX
0xXXXX
High impedance
1
WB
= 10 kΩ ± 100 Ω. See Table 2
Table 14
.
Last user command sent to the digipot
Prepares the SDO pin to be placed in high impedance mode
The SDO pin is placed in high impedance
Action
Table 11
Rev. D | Page 25 of 32
).
Keep the SYNC pin low until all 32 bits are clocked into their
respective serial registers. The SYNC pin is then pulled high to
complete the operation.
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented
the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5291 and AD5292 employ
a three-stage segmentation approach, as shown in Figure 65.
The AD5291 and AD5292 wiper switches are designed with the
transmission gate CMOS topology and with the gate voltages
derived from V
SCLK
CONTROLLER
ADDRESS
DECODER
8-/10-BIT
MICRO-
MOSI
SS
Figure 64. Daisy-Chain Configuration Using SDO
DD
and V
Figure 65. Simplified RDAC Circuit
DIN
SYNC
A
B
AD5291/
AD5292
U1
SS
.
SCLK
SDO
R
R
R
R
L
L
L
L
V
LOGIC
R
2.2kΩ
P
AD5291/AD5292
R
R
R
R
M
M
M
M
DIN
R
R
SYNC
W
W
AD5291/
AD5292
U2
S
W
SCLK
SDO
W