AD5171BRJZ5-R2 Analog Devices Inc, AD5171BRJZ5-R2 Datasheet - Page 14

• Manufacturer Part Number: AD5171BRJZ5-R2
• Description: IC DGTL POT OTP 5K I2C SOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD5171BRJZ5-R2

• Memory Type: Non-Volatile
• Temperature Coefficient: 35 ppm/°C Typical
• Taps: 64
• Resistance (ohms): 5K
• Number Of Circuits: 1
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Resistance In Ohms: 5K
• End To End Resistance: 5kohm
• Resistance Tolerance: ± 30%
• No. Of Steps: 64
• Control Interface: Serial, I2C, 2-Wire
• No. Of Pots: Single
• Supply Voltage Range: 2.7V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD5171EVAL - BOARD EVAL FOR AD5171
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: AD5171BRJZ5-R2TR

AD5171
Ignoring the effect of the wiper resistance, the transfer function
is simply
A more accurate calculation, which includes the wiper
resistance effect, yields
Unlike in rheostat mode where the absolute tolerance is high,
potentiometer mode yields an almost ratiometric function of
D/63 with a relatively small error contributed by the R
thus, the tolerance effect is almost cancelled. Although the thin
film step resistor (R
very different temperature coefficients, the ratiometric adjustment
also reduces the overall temperature coefficient effect to 5 ppm/°C,
except at low value codes where R
Potentiometer mode includes other operations such as op amp
input, feedback resistor networks, and voltage scaling applications.
Terminal A, Terminal W, and Terminal B can, in fact, be input
or output terminals provided that |V
exceed V
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the OTP and normal
operating voltage supplies share the same V
AD5171. The AD5171 employs fuse link technology that requires
4.75 V to 5.25 V for blowing the internal fuses to achieve a
given setting, but normal V
and 5.5 V after the fuse programming process. As a result, dual
voltage supplies and isolation are needed if system V
than the required V
an on-board regulator or rack-mount power supply) must be
rated at 4.75 V to 5.25 V and able to provide a 100 mA current
for 400 ms for successful one-time programming. Once fuse
programming is complete, the V
to allow normal operation at 2.7 V to 5.5 V; the device then
consumes current in the μA range.
Figure 29. 5 V OTP Supply Isolated from the 2.7 V Normal Operating Supply;
2.7V
5V
V
V
W
W
the V
(
(
10kΩ
DD
D
D
R1
)
)
to GND.
DD_OTP
=
=
P1 = P2 = FDV302P, NDS0610
P1
63
63
D
D
R
AB
supply must be removed once OTP is complete.
R
V
AB
A
+
S
DD_OTP
APPLY FOR OTP ONLY
) and CMOS switches resistance (R
P2
2
+
R
R
W
W
10µF
. The fuse programming supply (either
V
C1
DD
A
can be anywhere between 2.7 V
W
0.1µF
DD_OTP
dominates.
C2
AB
|, |V
supply must be removed
WA
DD
V
DD
|, and |V
terminal of the
AD5171
DD
W
WB
terms;
is lower
W
| do not
) have
Rev. D | Page 14 of 24
(3)
(4)
When operating at 2.7 V, use of the bidirectional low threshold
P-Ch MOSFETs is recommended for the isolation of the supply.
As shown in Figure 29, this assumes that the 2.7 V system
voltage is applied first, and the P1 and P2 gates are pulled to
ground, thus turning on P1 and, subsequently, P2. As a result,
V
is found, the factory tester applies the V
and the MOSFETs gates, thus turning off P1 and P2. The OTP
command should be executed at this time to program the
AD5171 while the 2.7 V source is protected. Once the fuse
programming is complete, the tester withdraws the V
the setting of the AD5171 is permanently fixed.
The AD5171 achieves the OTP function through blowing
internal fuses. Users should always apply the 4.75 V to
5.25 V one-time program voltage requirement at the first
fuse programming attempt. Failure to comply with this
requirement may lead to a change in the fuse structures,
rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × V
for Different Voltage Operation section.
Poor PCB layout introduces parasitics that may affect the fuse
programming. Therefore, it is recommended that a 10 μF
tantalum capacitor be added in parallel with a 1 nF ceramic
capacitor as close as possible to the V
chosen for both capacitors are important. This combination of
capacitor values provides both a fast response and larger supply
current handling with minimum supply droop during transients.
As a result, these capacitors increase the OTP programming
success by not inhibiting the proper energy needed to blow the
internal fuses. Additionally, C1 minimizes transient disturbance
and low frequency ripple, while C2 reduces high frequency
noise during normal operation.
ESD PROTECTION
Digital inputs SDA and SCL are protected with a series input
resistor and parallel Zener ESD structures (see Figure 30).
DD
of the AD5171 approaches 2.7 V. When the AD5171 setting
Figure 30. ESD Protection of Digital Pins
GND
340Ω
DD
and V
LOGIC
DD
. Refer to the Level Shifting
DD
DD_OTP
pin. The type and value
to both the V
DD_OTP
DD
and