AD5231BRU10 Analog Devices Inc, AD5231BRU10 Datasheet - Page 5

• Manufacturer Part Number: AD5231BRU10
• Description: IC DGTL POT 1024POS 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5231BRU10

• Rohs Status: RoHS non-compliant
• Taps: 1024
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 600 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 10K
• End To End Resistance: 10kohm
• Track Taper: Logarithmic
• Resistance Tolerance: +20, -40%
• No. Of Steps: 1024
• Supply Voltage Range: 2.7V To 5.5V, ± 2.25V To ± 2.75V
• Control Interface: Serial, SPI
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
V
Table 2.
Parameter
INTERFACE TIMING CHARACTERISTICS
FLASH/EE MEMORY RELIABILITY
1
2
3
4
5
6
7
8
derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.
Typical values represent average readings at 25°C and V
Guaranteed by design and not subject to production test.
See timing diagrams (Figure 3 and Figure 4) for location of measured values. All input control voltages are specified with t
from a voltage level of 1.5 V. Switching characteristics are measured using both V
Propagation delay depends on the value of V
Valid for commands that do not activate the RDY pin.
RDY pin low only for Instructions 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_2, 3 ~ 20 ms; CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.12 ms. Device operation at T
V
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
Retention lifetime equivalent at junction temperature (T
DD
DD
Clock Cycle Time (t
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay
CLK to SDO Data Hold Time
CS High Pulse Width
CS High to CS High
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store/Read EEMEM Time
Power-On EEMEM Restore Time
Dynamic EEMEM Restore Time
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous)
Preset Response Time to Wiper Setting
Endurance
Data Retention
< 3 V extends the EEMEM store time to 35 ms.
= 3 V to 5.5 V, V
7
8
CYC
SS
5
5
= 0 V, and −40°C < T
)
6
4
2, 3
DD
, R
PULL-UP
A
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
EEMEM1
EEMEM2
17
PRW
PRESP
< +85°C, unless otherwise noted.
, t
, and C
DD
J
5
) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
= 5 V.
L
.
Conditions
Clock level high or low
From positive CLK transition
From positive CLK transition
R
R
Applies to instructions 0x2, 0x3, and 0x9
R
R
Not shown in timing diagram
PR pulsed low to refresh wiper positions
P
P
AB
AB
= 2.2 kΩ, C
= 2.2 kΩ, C
= 10 kΩ
= 10 kΩ
Rev. C | Page 5 of 28
DD
L
L
= 3 V and V
< 20 pF
< 20 pF
DD
= 35 V.
R
= t
Min
20
10
1
10
5
5
0
10
4
0
10
50
100
F
= 2.5 ns (10% to 90% of 3 V) and timed
Typ
0.1
25
140
140
70
100
1
Max
40
50
50
0.15
AD5231
A
= −40°C and
Unit
ns
ns
t
ns
ns
ns
ns
ns
ns
ns
ns
t
ns
ms
ms
μs
μs
ns
ns
μs
kCycles
Years
CYC
CYC