CY7C1315KV18-250BZXC Cypress Semiconductor Corp, CY7C1315KV18-250BZXC Datasheet - Page 7

• Manufacturer Part Number: CY7C1315KV18-250BZXC
• Description: CY7C1315KV18-250BZXC
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY7C1315KV18-250BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pin Definitions
Document Number: 001-58904 Rev. *C
Pin Name
D
WPS
NWS
NWS
BWS
BWS
BWS
BWS
A
Q
RPS
C
C
K
K
CQ
[x:0]
[x:0]
0
1
2
3
0
1
,
,
,
,
,
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
Input clock
Input clock
Input clock
Input clock
Echo clock
Outputs-
Input-
Input-
Input-
Input-
Input-
Input-
I/O
Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
CY7C1311KV18  D
CY7C1911KV18  D
CY7C1313KV18  D
CY7C1315KV18  D
Write Port Select  Active LOW. Sampled on the rising edge of the K clock. When asserted active, a write
operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
Nibble Write Select 0, 1  Active LOW (CY7C1311KV18 only). Sampled on the rising edge of the K and
K clocks when write operations are active . Used to select which nibble is written into the device during
the current portion of the write operations. NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device .
Byte Write Select 0, 1, 2, and 3  Active LOW. Sampled on the rising edge of the K and K clocks when
write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1911KV18 BWS
CY7C1313KV18  BWS
CY7C1315KV18  BWS
BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device .
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2 M × 8 (4 arrays each of 512 K × 8) for CY7C1311KV18, 2 M × 9 (4 arrays each of 512 K × 9) for
CY7C1911KV18, 1 M × 18 (4 arrays each of 256 K × 18) for CY7C1313KV18 and 512 K × 36 (4 arrays
each of 128 K × 36) for CY7C1315KV18. Therefore, only 19 address inputs are needed to access the
entire memory array of CY7C1311KV18 and CY7C1911KV18, 18 address inputs for CY7C1313KV18 and
17 address inputs for CY7C1315KV18. These inputs are ignored when the appropriate port is deselected.
Data Output Signals. These pins drive out the requested data when the read operation is active. Valid
data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in
single clock mode. On deselecting the read port, Q
CY7C1311KV18  Q
CY7C1911KV18  Q
CY7C1313KV18  Q
CY7C1315KV18  Q
Read Port Select  Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
C clock. Each read access consists of a burst of four sequential transfers.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back to
the controller. See
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back to
the controller. See
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the
2
controls D
[26:18]
Application Example on page 11
Application Example on page 11
[7:0]
[8:0]
[17:0]
[35:0]
[7:0]
[8:0]
[17:0]
[35:0]
and BWS
0
0
0
controls D
controls D
controls D
[x:0]
[x:0]
when in single clock mode. All accesses are initiated on the rising edge of K.
when in single clock mode.
3
controls D
[8:0]
[8:0]
[8:0]
Switching Characteristics on page
, BWS
and BWS
Pin Description
[35:27].
1
controls D
0
CY7C1313KV18, CY7C1315KV18
controls D
CY7C1311KV18, CY7C1911KV18
1
[x:0]
controls D
for further details.
for further details.
are automatically tristated.
[17:9]
[3:0]
[17:9].
,
and NWS
26.
1
controls D
[7:4]
.
Page 7 of 33
[x:0]
.
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