PIC18F65K90-I/MR Microchip Technology, PIC18F65K90-I/MR Datasheet - Page 142

• Manufacturer Part Number: PIC18F65K90-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
REGISTER 10-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
REGISTER 10-13: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
DS39957D-page 142
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
CCP10IE
TMR5GIE
R/W-0
R/W-0
(1)
This bit is valid when the Type-B waveform with Non-Static mode is selected.
CCP10IE and CCP9IE are unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).
TMR5GIE: Timer5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
LCDIE: LCD Interrupt Enable bit
1 = Enabled
0 = Disabled
RC2IE: AUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
TX2IE: AUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
CTMUIE: CTMU Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP2IE: ECCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP1IE: ECCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
RTCCIE: RTCC Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP10IE:CCP3IE: CCP<10:3> Interrupt Enable bits
1 = Enabled
0 = Disabled
LCDIE
CCP9IE
R/W-0
R/W-0
(1)
(1)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
RC2IE
CCP8IE
R/W-0
R-0
(1)
CCP7IE
TX2IE
R/W-0
R-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CTMUIE
CCP6IE
R/W-0
R/W-0
(1)
CCP5IE
CCP2IE
R/W-0
R/W-0
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x = Bit is unknown
x = Bit is unknown
CCP1IE
CCP4IE
R/W-0
R/W-0
RTCCIE
CCP3IE
R/W-0
R/W-0
bit 0
bit 0