DAC101S101CIMK/NOPB National Semiconductor, DAC101S101CIMK/NOPB Datasheet - Page 2

• Manufacturer Part Number: DAC101S101CIMK/NOPB
• Description: IC CONV D-A 10BIT R-R TSOT-23-6
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DAC101S101CIMK/NOPB

• Settling Time: 5µs
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.41mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: TSOT-23-6, TSOT-6
• Number Of Channels: 1
• Resolution: 10b
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Resistor-String
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±2.8LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 6
• Package Type: TSOT
• For Use With: DAC101S101EVAL - BOARD EVALUATION DAC101S101
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DAC101S101CIMK; DAC101S101CIMKTR

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Ordering Information
Block Diagram
Pin Descriptions
(SOT-23)
Pin No.
TSOT
1
2
3
4
5
6
DAC101S101QCMKX
DAC101S101CIMMX
DAC101S101CIMKX
DAC101S101QCMK
DAC101S101CIMM
DAC101S101CIMK
DAC101S101EVAL
Order Numbers
Pin No.
MSOP
2, 3
4
8
1
7
6
5
−40°C
−40°C
−40°C
−40°C
−40°C
−40°C
Temperature Range
Evaluation Board
≤
≤
≤
≤
≤
≤
Symbol
SYNC
SCLK
T
T
T
T
T
T
V
GND
D
NC
A
A
A
A
A
A
V
OUT
IN
A
≤
≤
≤
≤
≤
≤
+105°C
+105°C
+105°C
+105°C
+125°C
+125°C
DAC Analog Output Voltage.
Ground reference for all on-chip circuitry.
Power supply and Reference input. Should be decoupled to GND.
Serial Data Input. Data is clocked into the 16-bit shift register on the falling
edges of SCLK after the fall of SYNC.
Serial Clock Input. Data is clocked into the input shift register on the falling
edges of this pin.
Frame synchronization input for the data input. When this pin goes low,
it enables the input shift register and data is transferred on the falling
edges of SCLK. The DAC is updated on the 16th clock cycle unless
SYNC is brought high before the 16th clock, in which case the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the
DAC.
No Connect. There is no internal connection to these pins.
2
MSOP T/R
TSOT T/R
TSOT T/R
Package
MSOP
TSOT
TSOT
TSOT
Top Mark
Q63C
X62C
X63C
Description
Grade Production Flow
Qualified; Automotive
20154103
AEC-Q100 Grade 1
Feature