CS4382A-DQZ Cirrus Logic Inc, CS4382A-DQZ Datasheet - Page 33

• Manufacturer Part Number: CS4382A-DQZ
• Description: IC DAC 8CH 114DB 192KHZ 48-LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4382A-DQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 680mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 84mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1524 - BOARD EVAL FOR CS4382A DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DS618F2
6. REGISTER DESCRIPTION
Note:
6.1
6.1.1
6.1.2
6.1.3
6.1.4
CPEN
7
0
All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted.
Mode Control 1 (Address 01h)
Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user
should write this bit within 10 ms following the release of Reset.
Freeze Controls (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneously,
enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
Master Clock Divide Enable (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
DAC Pair Disable (DACx_DIS)
Default = 0
0 - DAC Pair x Enabled
1 - DAC Pair x Disabled
Function:
When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate
the possibility of audible artifacts.
FREEZE
6
0
MCLKDIV
5
0
DAC4_DIS
4
0
DAC3_DIS
3
0
DAC2_DIS
2
0
DAC1_DIS
1
0
CS4382A
PDN
0
1
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