MT47H32M8BP-37E IT:B TR Micron Technology Inc, MT47H32M8BP-37E IT:B TR Datasheet - Page 16

• Manufacturer Part Number: MT47H32M8BP-37E IT:B TR
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M8BP-37E IT:B TR

• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 500ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 160mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions (Continued)
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
UDQS, UDQS#
RDQS, RDQS#
LDQS, LDQS#
Symbol
V
V
V
V
V
V
RFU
V
NU
NU
NC
NF
DDQ
SSDL
DDL
SSQ
REF
DD
SS
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Type
I/O
I/O
–
–
–
–
–
Description
Data strobe for lower byte: LDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command. Output with read data. Edge-aligned with read da-
ta. Input with write data. Center-aligned with write data.
Data strobe for upper byte: UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command. Output with read data. Edge-aligned with read da-
ta. Input with write data. Center-aligned with write data.
Redundant data strobe: For the x8 configuration only. RDQS is enabled/disabled via the
LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disabled, ball
B3 becomes data mask (see DM ball). RDQS# is only used when RDQS is enabled and differ-
ential data strobe mode is enabled.
Power supply: 1.8V ±0.1V.
DLL power supply: 1.8V ±0.1V.
DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity.
SSTL_18 reference voltage (V
Ground.
DLL ground: Isolated on the device from V
DQ ground: Isolated on the device for improved noise immunity.
No connect: These balls should be left unconnected.
No function: For the x4 configuration, these balls are no function. For the x8 configuration,
they are used as DQ[7:4].
Not used: If EMR(E10) = 0: For the x4 configuration, A2 = NU and A8 = NU. For the x8 con-
figuration, A2 = RDQS# and A8 = DQS#. If EMR(E10) = 1: For the x4 configuration, A2 = NU
and A8 = NU. For the x8 configuration, A2 = NU and A8 = NU.
Not Used: If EMR(E10) = 0: For the x16 configuration, A8 = UDQS# and E8 = LDQS#. If
EMR(E10) = 1: For the x16 configuration, A8 = NU and E8 = NU.
Reserved for future use: Bank address BA2, row address bits A[15:13].
DDQ
16
/2).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
SS
256Mb: x4, x8, x16 DDR2 SDRAM
and V
SSQ
.
©2003 Micron Technology, Inc. All rights reserved.