SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 119

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

SuperI/O Module
AMD Geode™ SC1200/SC1201 Processor Data Book
Bank 1, Offset 03h
This register is set to 00h on power-up of V
Bank 1, Offset 04h
Bank 1, Offset 05h
This register defines the station address to be compared with the address contained in the incoming CEIR message. If CEIR is enabled
(bit 0 of the IRWCR register is 1) and an address match occurs, then bit 5 of the WKSR register is set to 1.
This register is set to 00h on power-up of V
Bank 1, Offset 06h
Each bit in this register determines whether the corresponding bit in the IRWAD register takes part in the address comparison. Bits 5, 6,
and 7 must be set to 1 if the RC-5 protocol is selected.
This register is set to E0h on power-up of V
Bank 1, Offset 07h
This register holds the received address to be compared with the address contained in the IRWAD register.
This register is set to 00h on power-up of V
These two registers (IRWTR0L and IRWTR0H) define the low and high limits of time range 0 (see Table 5-26 on page 116). The values
are represented in units of 0.1 ms.
• RC-5 protocol: The bit cell width must fall within this range for the cell to be considered valid. The nominal cell width is 1.778 msec for
• NEC protocol: The time distance between two consecutive CEIR pulses that encodes a bit value of 0 must fall within this range. The
Bank 1, Offset 08h
This register is set to 10h on power-up of V
Bank 1, Offset 09h
This register is set to 14h on power-up of V
a 36 KHz carrier. IRWTR0L and IRWTR0H should be set to 10h and 14h, respectively. (Default)
nominal distance for a 0 is 1.125 msec for a 38 KHz carrier. IRWTR0L and IRWTR0H should be set to 09h and 0Dh, respectively.
Bit
7:6
5:4
7:0
7:0
7:0
7:5
4:0
7:5
4:0
3
2
1
0
Description
Reserved.
CEIR Protocol Select.
00: RC5
01: NEC/RCA
1x: Reserved
Reserved.
Invert IRRX Input.
0: Not inverted. (Default)
1: Inverted.
Reserved.
CEIR Enable.
0: Disable. (Default)
1: Enable.
CEIR Wakeup Address.
CEIR Wakeup Address Mask.
• If the corresponding bit is 0, the address bit is not masked (enabled for compare).
• If the corresponding bit is 1, the address bit is masked (ignored during compare).
CEIR Address.
Reserved.
CEIR Pulse Change, Range 0, Low Limit.
Reserved.
CEIR Pulse Change, Range 0, High Limit.
Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers
CEIR Wakeup Address Register - IRWAD (R/W)
CEIR Wakeup Control Register - IRWCR (R/W)
CEIR Wakeup Mask Register - IRWAM (R/W)
PP
PP
PP
PP
PP
PP
CEIR Address Shift Register - ADSR (RO)
or software reset.
or software reset.
or software reset.
or software reset.
or software reset.
or software reset.
CEIR Wakeup Range 0 Registers
IRWTR0L Register (R/W)
IRWTR0H Register (R/W)
Reserved
32579B
Reset Value: E0h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 10h
Reset Value: 14h
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