SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 150

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

6.2.5.5
DMA transfers occur between ISA I/O peripherals and sys-
tem memory (i.e., not available externally). The data width
can be either 8 or 16 bits. Out of the seven DMA channels
available, four are used for 8-bit transfers while the remain-
ing three are used for 16-bit transfers. One byte or WORD
is transferred in each DMA cycle.
Note: The Core Logic module does not support DMA
The ISA DMA device initiates a DMA request by asserting
one of the DRQ[7:5, 3:0] signals. When the Core Logic
module receives this request, it sends a bus grant request
150
transfers to ISA memory.
IOCHRDY
FRAME#
FRAME#
SD[15:0]
AD[31:0]
ISA DMA
SD[15:0]
AD[31:0]
MEMW#
PCICLK
IOCHRDY
PCICLK
MEMR#
ISACLK
ISACLK
TRDY#
TRDY#
IRDY#
IRDY#
IOW#
IOR#
32579B
Figure 6-4. ISA DMA Read from PCI Memory
Figure 6-5. ISA DMA Write to PCI Memory
to the PCI arbiter. After the PCI bus has been granted, the
respective DACK# is driven active.
The Core Logic module generates PCI memory read or
write cycles in response to a DMA cycle. Figure 6-4 and
Figure 6-5 are examples of DMA memory read and mem-
ory write cycles. Upon detection of the DMA controller’s
MEMR# or MEMW# active, the Core Logic module starts
the PCI cycle, asserts FRAME#, and negates an internal
IOCHRDY. This assures the DMA cycle does not complete
before the PCI cycle has provided or accepted the data.
IOCHRDY is internally asserted when IRDY# and TRDY#
are sampled active.
AMD Geode™ SC1200/SC1201 Processor Data Book
Core Logic Module