L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 6

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

Gigabit Ethernet Transceiver
Functional Description
Transmit Functions
1000Base-T Encoder
In 1000Base-T mode, the ET1011C translates 8-bit data
from the MAC interfaces into a code group of four quinary
symbols that are then transmitted by the PMA as 4D five-
level PAM signals over the four pairs of CAT-5 cable.
100Base-TX Encoder
In 100Base-TX mode, 4-bit data from the media independent
interface (MII) is 4B/5B encoded to output
5-bit serial data at 125 MHz. The bit stream is sent to a
scrambler, and then encoded to a three-level MLT3 sequence
that is then transmitted by the PMA.
10Base-T Encoder
In 10Base-T mode, the ET1011C transmits and receives
Manchester-encoded data.
Receive Functions
Decoder 1000Base-T
In 1000Base-T mode, the PMA recovers the 4D PAM signals
after compensating for the cabling conditions. The resulting
code group is decoded to 8-bit data. Data stream delimiters
are translated appropriately, and the data is output to the
receive data pins of the MAC
interfaces. The GMII receive error signal is asserted when
invalid code groups are detected in the data stream.
Decoder 100Base-TX
In 100Base-TX mode, the PMA recovers the three-level
MLT3 sequence that is descrambled and 5B/4B decoded to
4-bit data. This is output to the MII receive data pins after
data stream delimiters have been translated appropriately.
The MII receive error signal is asserted when invalid code
groups are detected in the data stream.
Decoder 10Base-T
In 10Base-T mode, the ET1011C decodes the Manchester-
encoded received signal.
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(continued)
Hybrid
The hybrid subtracts the transmitted signal from the input
signal allowing full-duplex operation on each of the twisted-
pair cables.
Programmable Gain Amplifier (PGA)
The PGA operates on the received signal in the analog
domain prior to the analog-to-digital converter (ADC). The
gain control module monitors the signal at the output of the
ADC in the digital domain to control the PGA. It implements
a gain that maximizes the signal at the ADC while ensuring
that no hard clipping occurs.
Clock Generator
A clock generator circuit uses the 25 MHz input clock signal
and a phase-locked loop (PLL) circuit to generate all the
required internal analog and digital clocks. A 125 MHz sys-
tem clock is also generated and is available as an output
clock.
Analog-to-Digital Converter
The ADC operates at 250 MHz oversampling at twice the
symbol rate in 1000Base-T and 100Base-TX. This enables
innovative timing recovery and fractional skew correction
and has allowed transfer of analog complexity to the digital
domain.
Timing Recovery/Generation
The timing recovery and generator block creates transmit
and receive clocks for all modes of operation. In transmit
mode, the 10Base-T and 100Base-TX modes use the 25
MHz clock input. While in receive mode, the input clock is
locked to the receive data stream. 1000Base-T is imple-
mented using a master-slave timing scheme, where the mas-
ter transmit and receive are locked to the 25 MHz clock
input, and the slave acquires timing information from the
receive data stream. Timing recovery is accomplished by
first acquiring lock on one channel and then making use of
the constant phase relationship between channels to lock on
the other pairs, resulting in a simplified PLL architecture.
Timing shifts due to changing environmental conditions are
tracked by the ET1011C.
September 2007
LSI Corporation