MT4LSDT864AG-10EG2 Micron Technology Inc, MT4LSDT864AG-10EG2 Datasheet
MT4LSDT864AG-10EG2
Specifications of MT4LSDT864AG-10EG2
Related parts for MT4LSDT864AG-10EG2
MT4LSDT864AG-10EG2 Summary of contents
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... SDRAM Unbuffered DIMM (UDIMM) MT4LSDT464A – 32MB MT4LSDT864A(I) – 64MB MT4LSDT1664A(I) – 128MB For component data sheets, refer to Micron’s Web site: Features • 168-pin, dual in-line memory module (DIMM) • PC100- and PC133-compliant • Unbuffered 2 • 32MB (4 Meg x 64) , 64MB (8 Meg x 64), 128MB (16 Meg x 64) • ...
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... MT4LSDT464AG-133_ 2 MT4LSDT464AY-133_ 2 MT4LSDT464AG-10E_ 1 MT4LSDT464AY-10E_ 1 MT4LSDT864AG-13E_ MT4LSDT864AY-13E_ 1 MT4LSDT864AIG-133_ 1 MT4LSDT864AG-133_ 1 MT4LSDT864AIY-133_ MT4LSDT864AY-133_ 2 MT4LSDT864AG-10E_ 1 MT4LSDT864AY-10E_ MT4LSDT1664AG-13E_ MT4LSDT1664AY-13E_ 1 MT4LSDT1664AIG-133_ MT4LSDT1664AG-133_ 1 MT4LSDT1664AIY-133_ MT4LSDT1664AY-133_ 2 MT4LSDT1664AG-10E_ 2 MT4LSDT1664AY-10E_ Notes: 1. Contact Micron for product availability. 2. Not recommended for new designs. 3. The designators for component and PCB revision are the last two characters of each part number ...
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... DNU 42 CK0 63 Notes: 1. Pin 126 is NC for 32MB and 64MB modules, or A12 for the 128MB module. Figure 2: Pin Locations (168-Pin DIMM) Front View PIN 1 Back View PIN 168 PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3 SD4C4_8_16X64AG.fm - Rev. D 1/07 EN 32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM ...
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... The address inputs also provide the op-code during a MODE REGISTER SET command. Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-detect address inputs: These pins are used to configure the presence-detect device. Input/Output ...
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... Supply Power supply: +3.3V ±0.3V. Supply Ground. – Do not use: These pins are not used on these modules, but are assigned pins on other modules in this product family. – Not connected: These pins are not connected on these modules. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... BA0–BA1 Notes: 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide found on Micron’s Web site: www.micron.com/support. 3. Standard modules use the following SDRAM devices: MT48LC4M16A2TG(IT) (32MB); ...
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... A0–A8 for 64MB and 128MB) are used to select the starting device column location for the burst access. These modules provide for programmable READ or WRITE burst lengths locations, or the full page with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...
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... M4–M6 specify the CAS latency, M7 and M8 specify the oper- ating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. For the 128MB module, address A12 (M12) is undefined but should be driven LOW during loading of the mode register. ...
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Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by ...
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... Figure 4: Mode Register Definition Diagram 32MB and 64MB Modules 128MB Module Notes: 1. M11 and M10 should be programmed = “0, 0” to ensure compatibility with future devices. 2. M12, M11, and M10 should be programmed = “0, 0, 0” to ensure compatibility with future devices. PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3 SD4C4_8_16X64AG ...
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Table 6: Burst Definition Table Burst Length Starting Column Address Full page ( A0–Ai (location Notes: 1. For full-page accesses 256 (32MB ...
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Figure 5: CAS Latency Diagram CLK COMMAND DQ CLK COMMAND DQ CAS Latency (CL the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency ...
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Table 7: CAS Latency Table Speed -13E -133 -10E PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3 SD4C4_8_16X64AG.fm - Rev. D 1/07 EN 32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM Allowable Operating Clock Frequency (MHz ≤133 ≤100 ≤100 Micron Technology, Inc., ...
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... Write enable/output enable Write inhibit/output High-Z Notes: 1. A0–A11 define the op-code written to the mode register, and for the 128MB module, A12 should be driven LOW. 2. A0–A11 (32MB and 64MB) or A0–A12 (128MB) provide device row address, and BA0, BA1 determine which device bank is made active. ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...
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Table 11: AC Functional Characteristics (Continued) Notes 11, 31; notes appear on page 20 Parameter Data-out to high-impedance from PRECHARGE command Table 12: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, ...
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Table 13: DC Electrical Characteristics and Operating Conditions Notes notes appear on page 20; V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Input leakage current: Any input ...
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I Specifications DD Table 14: I Specifications and Conditions – 32MB DD Notes 11, 13; notes appear on page 20; V Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE ...
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Table 16: I Specifications and Conditions – 128MB (Continued) DD Notes 11, 13; notes appear on page 20; V Parameter/Condition Auto refresh current: CS# = HIGH; CKE = HIGH Self refresh current: CKE ≤ 0.2V PDF: 09005aef8078bc7c/Source: ...
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Notes 1. All voltages referenced This parameter is sampled MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications ...
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... Refer to device data sheet for timing waveforms. 32. The value of 33. Leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes. PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3 SD4C4_8_16X64AG ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions, as indicated in Figure 6 on page ...
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Figure 7: Definition of Start and Stop SCL SDA Figure 8: Acknowledge Response from Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Table 17: EEPROM Device Select Code The most significant bit (b7) is sent first ...
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Figure 9: SPD EEPROM Timing Diagram SCL t SU:STA SDA IN SDA OUT Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic ...
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Table 20: Serial Presence-Detect EEPROM AC Operating Conditions (Continued) Notes appear below; All voltages referenced to V Parameter/Condition WRITE cycle time Notes avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and ...
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... Number of bytes used by Micron 1 Total number of SPD memory bytes 2 Memory type 3 Number of row addresses 4 Number of column addresses 5 Number of banks 6 Module data width 7 Module data width (continued) 8 Module voltage interface levels t 9 SDRAM cycle time SDRAM access from clock, ( Module configuration type 12 Refresh rate/type ...
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... Reserved 62 SPD revision 63 Checksum for bytes 0–62 64 Manufacturer’s JEDEC ID code 65–71 Manufacturer’s JEDEC ID code (continued) 72 Manufacturing location 73–90 Module part number (ASCII) 91 PCB identification code 92 Identification code (continued) 93 Year of manufacture in BCD 94 Week of manufacture in BCD 95–98 Module serial number 99– ...
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... FRONT VIEW 133.05 (5.256) 133.20 (5.244 6.35 (0.250) TYP 42.18 (1.661) 1.00 (0.039) R (2X) 115.57 (4.550) ® their respective owners. 28 Module Dimensions U5 U6 17.78 (0.700) TYP 3.25 (0.128) (2X) 3.00 (0.118) 1.00 (0.039) 1.27 (0.050) TYP TYP PIN 84 (PIN 168 ON BACKSIDE) Micron Technology, Inc., reserves the right to change products or specifications without notice. ...