LMH0070SQ National Semiconductor, LMH0070SQ Datasheet - Page 21

• Manufacturer Part Number: LMH0070SQ
• Manufacturer: National Semiconductor

Specifications of LMH0070SQ

• Number Of Elements: 1
• Number Of Receivers: 5
• Number Of Drivers: 1
• Input Type: CMOS
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 100mV
• Diff. Input Low Threshold Volt: -100mV
• Output Type: Serializer
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ADD
'h
27
28
29
2A
2B-2D
2E
2F
Name
Event Disable
LVDS LOS
Override Operation
LOS Status
Event Status
Reserved
Reverse Bit Order
Reserved
Bits
The SER keeps counts of various types of events. These include FIFO over/underflows, and loss
of the input signals or clocks. This register allows the user to mask these errors from being
counted.
7:5
4
3
2
1
0
These bits are used to force the LOS indicator regardless of the input signal level on the LVDS
pins.
7:2
1
0
Reading the LOS status register will provide a byte which has six bits which represent the
presence or absence of a signal at each of the LVDS inputs to the SER.
7:6
5
4:0
The event status register has two user readable bits which indicate if the device is locked, and if
there is a signal present on the TXCLK input.
7:4
3
2
1:0
This bit can be used to reverse the serialization order, however it will only work properly when
the device is NOT in DVB_ASI mode
7
6
5:0
Field
Reserved
PLL_CLK_disable
fifo_error_disable
TXCLK_detect_disa
ble
CLK_LOS_disable
Data_LOS_disable
Reserved
LVDS Preset LOS
LVDS Reset LOS
Reserved
LOS_CLK
LOS_Data
Reserved
TXCLK_detect
PLL_lock
Reserved
Reserved
Reverse Bit Order
Reserved
21
R/W
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r
r
r
r
r/w
Default
0'b
0'b
0'b
0'b
0'b
0'b
0'b
0'b
0'b
0'b
0'b
0'b
Description
1: Clock Error disabled
0: Clock Errors counted
1: FIFO Errors ignored
0: FIFO Errors counted
1: TXCLK Detect Errors ignored
0: TXCLK Detect Errors counted
1: CLK_LOS Errors ignored
0: CLK_LOS Errors counted
1: Data_LOS Errors ignored
0: Data_LOS Errors counted
LVDS Preset LOS
1: Forces LOS to be Low
0: normal mode
LVDS Reset LOS
(has priority over Preset)
1: Forces LOS to be High
0: normal mode
1: No clock present on TXCLK
0: Clock present
1:No data present
0: Data Present(one bit per TX channel)
1: TXCLK detected
0: TXCLK not detected
1: PLL locked
0: PLL not locked
1: reverses serialization order
0: normal order
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