DS4424N+T&R Maxim Integrated Products, DS4424N+T&R Datasheet - Page 3

• Manufacturer Part Number: DS4424N+T&R
• Description: IC DAC 7BIT 4CH 5.5V 14-TDFN
• Manufacturer: Maxim Integrated Products

Specifications of DS4424N+T&R

• Number Of Bits: 7
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -

OUTPUT CURRENT SOURCE CHARACTERISTICS (continued)
(V
AC ELECTRICAL CHARACTERISTICS
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: C
SCL Clock Frequency
Bus Free Time Between STOP
and START Conditions
Hold Time (Repeated) START
Condition
Low Period of SCL
High Period of SCL
Data Hold Time
Data Setup Time
START Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Setup Time
SDA and SCL Capacitive
Loading
Output Leakage Current at Zero
Current Setting
Output Current Differential
Linearity
Output Current Integral Linearity
Output Current Variation Due to
Power-Supply Change
Output Current Variation Due to
Output-Voltage Change
CC
CC
= +2.7V to +5.5V, T A = -40°C to +85°C.)
= +2.7V to +5.5V, T
PARAMETER
PARAMETER
All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Input resistors (R
Supply current specified with all outputs set to zero current setting. A0 and A1 are connected to GND. SDA and SCL are con-
nected to V
The output-voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.
Temperature drift excludes drift caused by external resistor.
Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 127.
Guaranteed by design.
Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I
B
—total capacitance of one bus line in pF.
Two-/Four-Channel, I
_______________________________________________________________________________________
CC
. Excludes current through R
A
= -40°C to +85°C.)
FS
) must be between the speciifed values to ensure the device meets its accuracy and linearity specifications.
SYMBOL
SYMBOL
t
t
t
t
t
HD:STA
DH:DAT
SU:STO
I
SU:DAT
SU:STA
t
t
ZERO
DNL
f
t
HIGH
LOW
INL
BUF
C
SCL
t
t
R
F
B
(Note 9)
(Note 10)
(Note 10)
(Note 10)
(Notes 6, 7)
(Notes 7, 8)
DC source
DC sink
DC source, V
DC sink, V
FS
resistors (I
OUT
OUT
RFS
CONDITIONS
CONDITIONS
measure at 1.2V
). Total current including I
measure at 1.2V
2
C, 7-Bit Sink/Source
RFS
20 + 0.1C
20 + 0.1C
is I
MIN
-0.5
MIN
100
1.3
0.6
1.3
0.6
0.6
0.6
-1
-1
0
0
Current DAC
CC
+ (2 x I
B
B
TYP
0.32
0.42
0.16
0.16
TYP
2
C standard-mode timing.
RFS
).
MAX
MAX
+0.5
400
300
300
400
0.9
+1
+1
UNITS
UNITS
%/V
%/V
LSB
LSB
kHz
μA
pF
μs
μs
μs
μs
μs
ns
μs
ns
ns
μs
3