LM5067MMX-1 National Semiconductor, LM5067MMX-1 Datasheet - Page 17

• Manufacturer Part Number: LM5067MMX-1
• Manufacturer: National Semiconductor

Specifications of LM5067MMX-1

• Linear Misc Type: Negative Voltage
• Family Name: LM5067-1
• Package Type: MSOP
• Operating Supply Voltage (min): -9V
• Operating Supply Voltage (max): -80V
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / Rohs Status: Not Compliant

MOSFET SELECTION
It is recommended that the external MOSFET (Q1) selection
be based on the following criteria:
-
system voltage (V
occur at V
inserted or removed.
-
on the current limit threshold (50 mV/R
load current, since the circuit can operate near the current
limit threshold continuously.
-
the current threshold for the circuit breaker function (100 mV/
R
-
the thermal properties, should be used to determine the max-
imum power dissipation threshold set by the R
The programmed maximum power dissipation should have a
reasonable margin from the maximum power defined by the
FET's SOA chart if the LM5067-2 is used since the FET will
be repeatedly stressed during fault restart cycles. The FET
manufacturer should be consulted for guidelines.
-
tion at maximum load current (I
its junction temperature above the manufacturer’s recom-
mendation.
If the device chosen for Q1 has a maximum V
than 13V, an external zener diode must be added from its gate
to source, with the zener voltage less than the maximum
V
at least 110 mA to conduct the GATE pull-down current during
startup and in the circuit breaker mode.
TIMER CAPACITOR, C
The TIMER pin capacitor (C
time delay, fault timeout period, and restart timing of the
LM5067-2.
A) Insertion Delay - Upon applying the system voltage
(V
during the insertion time (t1 in Figure 3) to allow ringing and
transients at V
to a circuit card plug-in is unique, the worst case settling time
must be determined for each application. The insertion time
starts when the operating voltage (VCC-VEE) reaches the
POR
source charges C
value is calculated from:
where t1 is the desired insertion delay. For example, if the
desired insertion delay is 250 ms, C
At the end of the insertion delay, C
a 1.5 mA current sink.
B) Fault Timeout Period - During turn-on of the output volt-
age, or upon detection of a fault condition where the current
limit and/or power limit circuits regulate the current through
Q1, C
The Fault Timeout Period is the time required for the TIMER
pin voltage to reach 4.0V above VEE, at which time Q1 is
switched off. The required capacitor value for the desired
Fault Timeout Period t
GS
S
SYS
).
The Pulsed Drain Current spec (I
The maximum continuous current rating should be based
The SOA (Safe Operating Area) chart of the device, and
The BV
R
rating. The zener diode’s forward current rating must be
IT
DS(on)
) to the circuit, the external MOSFET (Q1) is held off
T
threshold, at which time the internal 6 µA current
is charged by the fault timer current source (85 µA).
SYS
should be sufficiently low that the power dissipa-
DSS
SYS
when the circuit card, or adjacent cards, are
rating should be greater than the maximum
SYS
to settle. Since each backplane’s response
T
from 0V to 4.0V. The required capacitor
), plus ringing and transients which can
FAULT
T
T
is calculated from:
) sets the timing for the insertion
L(max)
T
2
DM
is quickly discharged by
T
x R
) must be greater than
calculates to 0.38 µF.
S
DS(on)
), not the maximum
) does not raise
GS
PWR
rating less
resistor.
17
For example, if the desired Fault Timeout Period is 16 ms,
C
is in use, C
µA current sink, after which a power up sequence can be ini-
tiated by external circuitry. See the Fault Timer and Restart
section and Figure 5. If the LM5067-2 is in use, after the Fault
Timeout Period expires a restart sequence begins as de-
scribed below (Restart Timing).
Since the LM5067 normally operates in power limit and/or
current limit during a power up sequence, the Fault Timeout
Period MUST be longer than the time required for the output
voltage to reach its final value. See the Turn-on Time section.
C) Restart Timing If the LM5067-2 is in use, after the Fault
Timeout Period described above, C
µA current sink to 1.25V. The TIMER pin then cycles through
seven additional charge/discharge cycles between 1.25V and
4.0V as shown in Figure 6. The restart time ends when the
TIMER pin voltage reaches 0.3V during the final high-to-low
ramp. The restart time, after the Fault Timeout Period, is equal
to:
For example, if C
end of the restart time, Q1 is switched on. If the fault is still
present, the fault timeout and restart sequence repeats. The
on-time duty cycle of Q1 is approximately 0.5% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the
LM5067 enables the series pass device (Q1) when the input
supply voltage (V
If V
threshold, Q1 is switched off, denying power to the load. Hys-
teresis is provided for each threshold.
Note: All voltages are with respect to Vee in the discus-
sions below. Use absolute values in the equations.
Option A: The configuration shown in Figure 11 requires
three resistors (R1-R3) to set the thresholds.
FIGURE 11. UVLO and OVLO Thresholds Set By R1-R3
T
calculates to 0.34 µF. After a fault timeout, if the LM5067-1
SYS
is below the UVLO threshold, or above the OVLO
T
must be allowed to discharge to <0.3V by the 2.5
T
SYS
= 0.33 µF, t
) is within the desired operational range.
= C
T
x 9.4 x 10
RESTART
T
is discharged by the 2.5
6
= 3.1 seconds. At the
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