MT47H128M8HQ-3:E T/R Micron Technology Inc, MT47H128M8HQ-3:E T/R Datasheet - Page 55

• Manufacturer Part Number: MT47H128M8HQ-3:E T/R
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3:E T/R

• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 27: AC Input Test Conditions
PDF: 09005aef821ae8bf
Rev. O 9/08 EN
Parameter
Input setup timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
Input hold timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
Input timing measurement reference level (single-
ended) DQS for x4, x8; UDQS, LDQS for x16
Input timing measurement reference level (differential)
CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,
RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16
Notes:
1. All voltages referenced to Vss.
2. Input waveform setup timing (
3. See Input Slew Rate Derating (page 56).
4. The slew rate for single-ended inputs is measured from DC level to AC level, Vil(DC) to
5. Input waveform hold (
6. Input waveform setup timing (
7. Input waveform setup timing (
8. Input waveform timing is referenced to the crossing point level (Vix) of two input sig-
9. The slew rate for differentially ended inputs is measured from twice the DC level to
Vih(AC) level for a rising signal and Vil(AC) for a falling signal applied to the device un-
der test, as shown in Figure 30 (page 68).
Vih(AC) on the rising edge and Vil(AC) to Vih(DC) on the falling edge. For signals refer-
enced to Vref, the valid intersection is where the “tangent” line intersects Vref, as
shown in Figure 23 (page 59), Figure 25 (page 61), Figure 27 (page 66), and Fig-
ure 29 (page 67).
Vil(DC) level for a rising signal and Vih(DC) for a falling signal applied to the device un-
der test, as shown in Figure 30 (page 68).
referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to
the device under test, as shown in Figure 32 (page 69).
is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/
LDQS#, as shown in Figure 31 (page 68).
nals (Vtr and Vcp) applied to the device under test, where Vtr is the true input signal
and Vcp is the complementary input signal, as shown in Figure 33 (page 69).
twice the AC level: 2 × Vil(DC) to 2 × Vih(AC) on the rising edge and 2 × Vil(AC) to 2 ×
Vih(DC) on the falling edge. For example, the CK/CK# would be –250mV to +500mV for
CK rising edge and would be +250mV to –500mV for CK falling edge.
t
IH
b
55
Vref(DC)
Symbol
) timing is referenced from the input signal crossing at the
Vrh
Vrd
Vrs
AC Overshoot/Undershoot Specification
t
t
t
IS
DS) and hold timing (
DS) and hold timing (
b
) is referenced from the input signal crossing at the
Micron Technology, Inc. reserves the right to change products or specifications without notice.
VddQ ×
Min
0.49
1Gb: x4, x8, x16 DDR2 SDRAM
See Note 2
See Note 5
Vix(AC)
VddQ ×
t
t
DH) for single-ended data strobe is
DH) when differential data strobe
Max
0.51
© 2004 Micron Technology, Inc. All rights reserved.
Units
V
V
1, 3, 7, 8, 9
1, 2, 3, 4
1, 3, 4, 5
1, 3, 4, 6
Notes