MT47H128M8HQ-187EIT:G Micron Technology Inc, MT47H128M8HQ-187EIT:G Datasheet
MT47H128M8HQ-187EIT:G
Specifications of MT47H128M8HQ-187EIT:G
Related parts for MT47H128M8HQ-187EIT:G
MT47H128M8HQ-187EIT:G Summary of contents
Page 1
... Operating temperature – Commercial (0°C T – Industrial (–40°C T –40°C T – Automotive (–40°C T +105ºC) • Revision Note: 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM 1 +85°C) C +95°C; C +85° ...
Page 2
... Low power IT Industrial temperature AT Automotive temperature Speed Grade 1.875ns -187E 2.5ns -25E 2.5ns - 3ns - 3ns 3.75ns -37E 2 1Gb: x4, x8, x16 DDR2 SDRAM 800 1066 800 n/a 800 n/a n/a n/a n/a n/a n/a n/a 64 Meg Meg banks 8K A[13:0] (16K) A[12:0] (8K) ...
Page 3
... For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features ...
Page 4
... Output Drive Strength ................................................................................................................................ 85 DQS# Enable/Disable ................................................................................................................................. 85 RDQS Enable/Disable ................................................................................................................................. 85 Output Enable/Disable ............................................................................................................................... 85 On-Die Termination (ODT) ......................................................................................................................... 86 PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 5
... CKE Low Anytime ...................................................................................................................................... 128 ODT Timing .................................................................................................................................................. 130 MRS Command to ODT Update Delay ........................................................................................................ 132 PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 6
... Figure 49: READ-to-WRITE ............................................................................................................................ 99 Figure 50: READ-to-PRECHARGE – ..................................................................................................... 100 PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev ............................................................................................................... .............................................................................................................. ............................................................................................................. ............................................................................................................. 70 t RCD (MIN) .............................................................................. 93 6 1Gb: x4, x8, x16 DDR2 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. Features ...
Page 7
... DQSQ, QH, and Data Valid Window .................................................. 104 t t DQSQ, QH, and Data Valid Window ..................................................... 105 and DQSCK ......................................................................................... 106 7 1Gb: x4, x8, x16 DDR2 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. Features ...
Page 8
... Table 42: READ Using Concurrent Auto Precharge ......................................................................................... 101 Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 107 Table 44: Truth Table – CKE .......................................................................................................................... 122 PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev DS, DH Derating Values with Differential Strobe ............................................. 1Gb: x4, x8, x16 DDR2 SDRAM and IH) .................................................... and IH) ........................................... 62 t and DH ...
Page 9
... Bank active READ WRITE PRE, PRE_A Precharging identify all timing requirements or possible command restrictions such as multibank in- teraction, power down, entry/exit, etc. 9 1Gb: x4, x8, x16 DDR2 SDRAM State Diagram CKE_L Self refreshing REFRESH Refreshing Precharge power- down CKE_L ACT = ACTIVATE ...
Page 10
... I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs ...
Page 11
... Any specific requirement takes precedence over a general statement. PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM values must be derated when T DD via 1k * resistor DD via 1k * resistor ...
Page 12
... Functional Block Diagrams The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory inter- nally configured as a multibank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram ODT CKE Control CK logic CK# CS# RAS# CAS# WE# Refresh Mode 14 counter registers address 17 14 A0–A13, Address 17 BA0– ...
Page 13
... I/O gating DM mask logic Bank control 256 logic (x32) Column CK,CK# decoder Column- 8 address 2 counter/ latch COL0, COL1 13 1Gb: x4, x8, x16 DDR2 SDRAM Functional Block Diagrams ODT control CK, CK# COL0, COL1 sw1 sw2 8 DLL 8 sw1 sw2 8 32 Read 8 DRVRS R1 MUX latch ...
Page 14
... Column CK out CK, CK# decoder Column- 8 address 2 counter/ latch COL0, COL1 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Functional Block Diagrams ODT control CK, CK# COL0, COL1 sw1 sw2 16 DLL 16 sw1 sw2 16 16 DRVRS ...
Page 15
... V NC, RDQS#/ DM, DM/RDQS SSQ DQ1 V DDQ V DQ3 SSQ V V REF SS CKE WE# BA0 BA1 A10 A12 RFU 15 1Gb: x4, x8, x16 DDR2 SDRAM Ball Assignments and Descriptions DQS#/NU SSQ DDQ DQS V NF, DQ7 SSQ V DQ0 V DDQ DDQ DQ2 V NF, DQ5 SSQ SSDL DD RAS# ...
Page 16
... SS V LDM SSQ DQ1 V DDQ V DQ3 SSQ V V REF SS CKE WE# BA0 BA1 A10 A12 RFU DD 16 1Gb: x4, x8, x16 DDR2 SDRAM Ball Assignments and Descriptions UDQS#/NU SSQ DDQ UDQS V DQ15 SSQ V DQ8 V DDQ DDQ DQ10 V DQ13 SSQ V V LDQS#/NU SSQ DDQ ...
Page 17
... Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls: DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#, RDQS, RDQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input will be ignored if disabled via the LOAD MODE command ...
Page 18
... Not used: For x8 only. If EMR(E10 and E8 are RDQS# and DQS#. If EMR(E10 then A2 and E8 are not used. RFU – Reserved for future use: Row address bits A13 (x16 only), A14, and A15. PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM Ball Assignments and Descriptions /2). DDQ and ...
Page 19
... 0.8 TYP 6.4 CTR 8 ±0.1 36%Pb, 2% Ag). 19 1Gb: x4, x8, x16 DDR2 SDRAM Seating plane 0.12 A 1.1 ±0.1 0.25 MIN Exposed gold plated pad 1.0 MAX X 0.7 nominal. Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 20
... CTR 1.0 MAX X 0.7 nonconductive 8 ±0.1 floating pad 36%Pb, 2% Ag). 20 1Gb: x4, x8, x16 DDR2 SDRAM Ball A1 ID 1.2 MAX 0.25 MIN Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. Packaging ...
Page 21
... 0.8 TYP 6.4 CTR 8 ±0.1 36%Pb, 2% Ag). 21 1Gb: x4, x8, x16 DDR2 SDRAM Seating plane 0.12 A 1.1 ±0.1 0.25 MIN Exposed gold plated pad 1.0 MAX X 0.7 nominal. Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 22
... Rev 1.8V ±0.1V 25° / OUT(DC) DDQ OUT balls, reflecting the fact that they are matched in loading. any given device. C are not pass/fail parameters; they are targets. 22 1Gb: x4, x8, x16 DDR2 SDRAM Symbol Min Max Units Notes C 1 – DCK C 1 – ...
Page 23
... TN-00-08, ces listed in Table 7. For designs that are expected to last several years and require the flexibility to use several DRAM die shrinks, consider using final target theta values (rath- er than existing values) to account for increased thermal impedances from the die size reduction. The DDR2 SDRAM device’ ...
Page 24
... Figure 11. This case temperature limit is allowed to be exceeded briefly during pack- age reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Pa- rameters.” in Figure 11. tion. Length (L) 0.5 (L) 0.5 (W) Width (W) Lmm x Wmm FBGA 24 1Gb: x4, x8, x16 DDR2 SDRAM Min Max Units T –55 150 STG ...
Page 25
... DDR2 SDRAM JA (°C/W) Airflow = 2m/s JB (°C/W) 43.1 30.3 36.4 30 39.3 26.1 32.8 26.1 49.5 35.6 42.3 35.2 46.5 32.5 39 ...
Page 26
... Defined by pattern in Table 9 (page 27) Defined by pattern in Table 9 (page 27) 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM DD -3E -3 -37E 7.5 7.5 7 ...
Page 27
... RA7 active read auto precharge deselect. Notes: 2. All banks are being interleaved at 3. Control and address bus inputs are stable during deselects. PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM Electrical Specifications – Where general I DD7 without violating ...
Page 28
... DD1 x16 210 I x4, x8, x16 DD2P I x4, x8 DD2Q x16 I x4, x8 DD2N x16 I Fast exit DD3Pf MR12 = 0 I Slow exit DD3Ps MR12 = 1 I x4, x8 DD3N x16 28 1Gb: x4, x8, x16 DDR2 SDRAM DD -25E/ -3E/ -25 -3 -37E 150 135 110 110 100 95 175 130 120 ...
Page 29
... DD6L I x4, x8 DD7 x16 ); specifications are tested after the device is properly initialized. 0° 1.8V ±0.1V 1.8V ±0.1V DDQ parameters are specified with ODT disabled 1Gb: x4, x8, x16 DDR2 SDRAM DD -25E/ -3E/ -25 -3 -37E 190 145 120 110 210 160 135 125 405 ...
Page 30
... DD2N DD2Q T 85° 2%; I must be derated by 20 DD2P 30%; and I must be derated by 80% (I DD6 T < 85°C and the 2X refresh option is still enabled 1Gb: x4, x8, x16 DDR2 SDRAM DD limits increase) on IT-option and AT-option DD T 85°C: C and I DD4R DD5W must be derated by 7% DD7 , ...
Page 31
... DD t RAS = RAS I x4, x8, x16 DD2P I x4, x8 DD2Q ); CKE x4, x8 DD2N I Fast exit DD3Pf MR12 = 0 I Slow exit DD3Ps MR12 = 1 I x4, x8 DD3N ), ,x8 DD4W t RAS MAX 31 1Gb: x4, x8, x16 DDR2 SDRAM -25E/ -187E - x16 100 80 100 75 x16 115 x16 x16 x16 45 ...
Page 32
... DD devices when operated outside of the range 0°C When I and I must be derated by 4%; I DD2P DD3P(SLOW) T 0° 2%; and I and I C DD6 32 1Gb: x4, x8, x16 DDR2 SDRAM -25E/ -187E -25 150 120 x16 190 150 180 145 x16 210 150 7 7 ...
Page 33
... DD3N T 85° 2%; I must be derated by 20 DD2P 30%; and I must be derated by 80% (I DD6 T < 85°C and the 2X refresh option is still enabled 1Gb: x4, x8, x16 DDR2 SDRAM and I DD3P(FAST) DD4R DD4W DD5W must be derated by DD3P(SLOW) will increase by this amount if DD6 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 34
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications Clock 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 35
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev Timing Operating Specifications Jitter Clock 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Strobe-Out Data ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 36
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev Timing Operating Specifications Strobe-In Data 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 37
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev Timing Operating Specifications Data-Out 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Data-In ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 38
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications Address and Command 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 39
... Address PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN and Command 39 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications Refresh Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 40
... Refresh Self PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications Power-Down 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 41
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications ODT 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 42
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 43
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 44
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 45
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 46
... DC value. Peak-to-peak AC noise This measurement taken at the nearest V REF(DC) is not applied directly to the device sistors, is expected to be set equal REF 46 1Gb: x4, x8, x16 DDR2 SDRAM AC and DC Operating Conditions Nom Max 1.8 1.9 1.8 1.9 1.8 1.9 0.50 × V 0.51 × ...
Page 47
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev DDQ and R are determined by separately applying V TT1(EFF) TT2(EFF) being tested, and then measuring current, I(V ate between –40°C and 0° 1Gb: x4, x8, x16 DDR2 SDRAM ODT DC Electrical Characteristics Symbol Min Nom Max TT1(EFF) R 120 ...
Page 48
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN Input Electrical Characteristics and Operating Conditions Symbol V V IH(DC) V IL(DC) + 300mV allowed provided 1.9V is not exceeded. DDQ Symbol 1Gb: x4, x8, x16 DDR2 SDRAM Min Max 1 + 125 V REF(DC) DDQ –300 V - 125 REF(DC) Min Max V + 250 V IH(AC) ...
Page 49
... DQS) level and V is expected to be approximately 0.5 × 300mV allowed provided 1.9V is not exceeded. DDQ X X RDQS#, LDQS#, and UDQS# signals. V /2. DDQ ID(DC)min 49 1Gb: x4, x8, x16 DDR2 SDRAM Max V DDQ V DDQ V DDQ - 175 0.50 × 175 DDQ ...
Page 50
... Numbers in diagram reflect nominal values (V PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN Input Electrical Characteristics and Operating Conditions 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM = 1.8V). DDQ ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 51
... SSTL_18 receiver. The actual current val- IL,max ues are derived by shifting the desired driver operating point (see output IV curves) along a 21 load line to define a convenient driver current for measurement. 51 1Gb: x4, x8, x16 DDR2 SDRAM Max - 125 0.50 × 125 ...
Page 52
... V teed by design and characterization. 40°C and 0° DDQ 25 Reference point ) 52 1Gb: x4, x8, x16 DDR2 SDRAM Nom Max – 4 – 5 +85° 1.8V ±0.1V 1.8V ±0.1V. DDQ DD /I must be less than 23.4 for values of V OUT ...
Page 53
... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 5.63 11.30 16.52 22.19 27.59 32.39 36.45 40.38 44.01 47.01 49.63 51.71 53.32 54 ...
Page 54
... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 –5.63 –11.30 –16.52 –22.19 –27.59 –32.39 –36.45 –40.38 –44.01 –47.01 –49.63 –51.71 –53.32 – ...
Page 55
... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 2.98 5.99 8.75 11.76 14.62 17.17 19.32 21.40 23.32 24.92 26.30 27.41 28.26 29 ...
Page 56
... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 –2.98 –5.99 –8.75 –11.76 –14.62 –17.17 –19.32 –21.40 –23.32 –24.92 –26.30 –27.41 –28.26 – ...
Page 57
... Voltage Across Clamp (V) 57 1Gb: x4, x8, x16 DDR2 SDRAM Minimum Ground Clamp Current (mA) 0.0 0.0 0.0 0.0 0.0 ...
Page 58
... Figure 21) 0.19 Vns DDQ (see Figure 22) 0.19 Vns SSQ Maximum amplitude DDQ SSQ Time (ns) SSQ Maximum amplitude Time (ns) 58 1Gb: x4, x8, x16 DDR2 SDRAM Specification -25/-25E -3/-3E 0.50V 0.50V 0.50V 0.50V 0.50V 0.50V 0.66 Vns 0.80 Vns 0.66 Vns 0.80 Vns ...
Page 59
... AC level: 2 × × V IL(DC the falling edge. For example, the CK/CK# would be –250mV to 500mV for CK IH(DC) rising edge and would be 250mV to –500mV for CK falling edge. 59 1Gb: x4, x8, x16 DDR2 SDRAM Min Max Units See Note 2 See Note 5 V × 0.49 V × ...
Page 60
... REF(DC the time of the rising clock transition), a valid in- IH[AC] IL[AC] 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating t IH (hold time) required is calculated and IH derating ...
Page 61
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating and IH) CK, CK# Differential Slew Rate 2.0 V/ns 1.5 V/ 187 94 ...
Page 62
... DDR2 SDRAM Input Slew Rate Derating and IH) 1.0 V/ 210 154 203 149 193 143 180 135 160 105 ...
Page 63
... Setup slew rate REF(DC) IL(AC)max = rising signal REF Nominal region line Tangent line Nominal line TF SS Setup slew rate = rising signal 63 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate REF region IH(AC)min REF(DC Tangent line REF region TR Tangent line (V ...
Page 64
... CK CK DDQ REF region Tangent line Nominal Tangent line ( Hold slew rate REF[DC] IL[DC]max = falling signal TR 64 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate REF region Nominal line Tangent line REF line region TF Tangent line ( IH[DC]min ...
Page 65
... AC/DC trip points to DQ referenced to V Table 36 (page 68). Table 35 provides the and DH ) for DDR2-533. Table 36 provides the the and DH ) for DDR2-400 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating 1.4 V/ns 1.2 V/ns 1.0 V/ – – – – – – ...
Page 66
... DS and DH . Converting the derated base values from DQ referenced the AC/DC trip points to DQ referenced to V ble 34 provides the V -based fully derated values for the DQ ( REF 66 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating 1.4 V/ns 1.2 V/ns 1.0 V/ ...
Page 67
... DDR2 SDRAM Input Slew Rate Derating and and DH -specified values REF 1.0 V/ns 0.8 V/ns 0.6 V/ns ...
Page 68
... Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating ) at DDR2-533 REF ) REF 1.0 V/ns 0.8 V/ns 0.6 V/ ...
Page 69
... REF line region Tangent line Tangent line Nominal line TF TR Tangent line ( Tangent line (V REF[DC] IL[AC]max Setup slew rate = = rising signal TF 69 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate REF region IH(AC)min REF(DC and V IL(DC)max IH(DC)min t ...
Page 70
... DDQ REF region Tangent line Nominal Tangent line ( REF[DC] IL[DC]max Hold slew rate = TR falling signal 70 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate REF region IH(DC)min REF(DC and V IL(DC)max IH(DC)min Nominal line Tangent line REF ...
Page 71
... DQS# DQS Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)min V IL(AC)min V SSQ V DDQ V IH(AC)min V IH(DC)min V REF(DC) VIL(DC)max VIL(AC)max V SSQ ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 72
... DDQ Crossing point Vswing SSQ 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating V REF V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V SSQ ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 73
... H Power-down exit L 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at Notes: 2. The state of ODT does not affect the states described in this table. The ODT function is 3. “X” means “H or L” (but a defined logic level) for valid I 4 ...
Page 74
... Issue DESELECT or NOP commands, or allowable commands to the other bank, on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and this table, and according to Table 39 (page 76). 74 1Gb: x4, x8, x16 DDR2 SDRAM Command/Action t RP has been met, and any READ burst is com- t RCD has been met ...
Page 75
... NOP commands must be applied on each positive clock edge during these states): Refresh: Starts with registration of a REFRESH command and ends when t met. After RFC is met, the DDR2 SDRAM will be in the all banks idle state. Accessing Starts with registration of the LOAD MODE command and ends when t mode MRD has been met ...
Page 76
... A READ burst has been initiated with auto precharge disabled and has not yet terminated. Write: A WRITE burst has been initiated with auto precharge disabled and has not yet terminated. 76 1Gb: x4, x8, x16 DDR2 SDRAM Command/Action t RP has been met, and any READ t RCD has been met. ...
Page 77
... WRITE or WRITE with auto precharge DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT. PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN ...
Page 78
... If auto precharge is selected, the row being accessed will be pre- charged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to command to the internal device by AL clock cycles. ...
Page 79
... Mode Register (MR) The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CAS latency, operat- ing mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 35 (page 80) ...
Page 80
... Burst Length Burst length is defined by bits M0–M2, as shown in Figure 35. Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE command. ...
Page 81
... Figure 35 (page 80). When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is “1.” ...
Page 82
... Write Recovery Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 35 (page 80). The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera- tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter- nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last data burst. An example of WRITE with auto precharge is shown in Figure 64 (page 114). WR values clocks may be used for programming bits M9– ...
Page 83
... DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea- ture allows the READ command to be issued prior to nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further detail in Posted CAS Additive Latency (AL) (page 86). Examples and are shown in Figure 36; both assume READ command is registered at clock edge n, and the clocks, the data will be available nominally coincident with clock edge (this assumes ...
Page 84
... OCD operation, all three bits must be set to “1” for the OCD default state, then set to “0” before initialization is finished. 84 1Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR) t MRD before initiating any subsequent opera- ...
Page 85
... The output disable feature is intended to be used during I characterization of read current. DD PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev DQSCK parameters. 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR) ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 86
... In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to using this feature would set held for the time of the AL before it is issued internally to the DDR2 SDRAM device controlled by the sum of AL and CL CL. WRITE latency (WL) is equal to RL minus one clock × ...
Page 87
... ACTIVE n WRITE n DQS, DQS Notes PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev NOP NOP NOP AC, DQSCK, and T2 T3 NOP NOP t RCD (MIN 1Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR NOP NOP NOP Transitioning Data t DQSQ NOP NOP NOP Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ ...
Page 88
... Extended mode register (EMR2) Extended mode register (EMR3) grammed to “0.” served for future use and must be programmed to “0.” 88 1Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register 2 (EMR2) t MRD before initiating any subsequent opera Address bus ...
Page 89
... Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) programmed to “0.” served for future use and must be programmed to “0.” 89 1Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register 3 (EMR3) t MRD before initiating any subsequent opera Address bus ...
Page 90
... PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev. W 7/11 EN 1Gb: x4, x8, x16 DDR2 SDRAM 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. Initialization ‹ 2007 Micron Technology, Inc. All rights reserved. ...
Page 91
... TT to the ODT ball (all other inputs may be undefined; I/Os and outputs must be less than V during voltage ramp time to avoid DDR2 SDRAM device latch-up). V DDQ plied directly to the device; however, least one of the following two sets of conditions ( must be met to obtain a stable ...
Page 92
... Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, 13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and 14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles af- 15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configura- 16 ...
Page 93
... ACTIVATE Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated. ...
Page 94
... READ Row Col Row Col Bank b Bank b Bank c Bank c t FAW (MIN 3.75ns FAW (MIN) = 37.5ns. 94 1Gb: x4, x8, x16 DDR2 SDRAM ACT READ NOP NOP Row Col Bank d Bank d t RRD (MIN) = 7.5ns, Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 95
... READ burst as long as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of DDR2 SDRAM. As shown in Figure 48 (page 99), READ burst operations may not be interrupted or truncated with any other command except another READ com- mand. ...
Page 96
... READ NOP NOP Bank a, Col ( READ NOP NOP Bank a, Col ( AC, DQSCK, and 96 1Gb: x4, x8, x16 DDR2 SDRAM T3 T3n T4 T4n NOP NOP T4n NOP NOP T3n T4 T4n NOP NOP DO n Transitioning Data t DQSQ. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 97
... READ Bank, Bank, Col n Col b t CCD READ NOP READ Bank, Bank, Col n Col b t CCD AC, DQSCK, and 97 1Gb: x4, x8, x16 DDR2 SDRAM T5n T3 T3n T4 T4n T5 NOP NOP NOP T5n T2n T3 T3n T4 T4n T5 NOP NOP NOP DO n Transitioning Data t DQSQ. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 98
... NOP READ Bank, Bank, Col n Col READ NOP NOP READ Bank, Bank, Col n Col AC, DQSCK, and tive READs. 98 1Gb: x4, x8, x16 DDR2 SDRAM T3n T4 T4n T5 T6 T6n T7 NOP NOP NOP NOP T4n T5 T5n NOP NOP NOP NOP DO n Transitioning Data t DQSQ. ...
Page 99
... T2 can be either same bank or different bank). terrupting READ command. t DQSQ NOP NOP WRITE AC, DQSCK, and t RTP is the minimum time from the rising clock edge that initiates the last 4-bit 99 1Gb: x4, x8, x16 DDR2 SDRAM Valid Valid Valid Transitioning Data t CK from previous READ. t AC, ...
Page 100
... READ NOP NOP NOP AL + BL/2 - 2CK + MAX ( t RTP 2CK) Bank •t RAS (MIN) •t RC (MIN) t RTP 2 clocks AC, DQSCK, and 100 1Gb: x4, x8, x16 DDR2 SDRAM NOP NOP ACT Bank a Valid • (MIN) Transitioning Data Don’t Care t DQSQ NOP PRE ...
Page 101
... READ with Auto Precharge If A10 is high when a READ command is issued, the READ with auto precharge function is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock edge that (BL/2) cycles later than the read with auto precharge command provi- t ded edge, the start point of the auto precharge operation will be delayed until satisfied ...
Page 102
... CK NOP 1 NOP 1 READ 2 Col n 5 Bank x t RCD RAS these times. but to when the device begins to drive or no longer drives, respectively. order. 102 1Gb: x4, x8, x16 DDR2 SDRAM T7n T8 NOP 1 PRE 3 NOP 1 NOP 1 t RTP 4 All banks One bank Bank ...
Page 103
... NOP commands are shown for ease of illustration; other commands may be valid at Notes ( the case shown. 3. The DDR2 SDRAM internally delays auto precharge until both 4. Enable auto precharge. 5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level data-out from column n; subsequent elements are applied in the programmed PDF: 09005aef821ae8bf 1GbDDR2.pdf – ...
Page 104
... DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transitions, and ends with the last valid transition of DQ. T2 and at T2n are “early DQS,” are “nominal DQS,” and at T3n are “late DQS.” derived from HP 104 1Gb: x4, x8, x16 DDR2 SDRAM T2n T3 T3n DQSQ 2 t DQSQ 2 t DQSQ ...
Page 105
... CH clock transitions collectively when a bank is active. t DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transitions, and ends with the last valid transition of DQ. lower byte, and UDQS defines the upper byte. 105 1Gb: x4, x8, x16 DDR2 SDRAM T3 T3n ...
Page 106
... I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level, WRITE WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL minus one clock cycle ( 1CK) (see READ (page 78)). The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...
Page 107
... WRITE burst as long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture of DDR2 SDRAM. WRITE burst operations may not be interrupted or truncated with any command except another WRITE command, as shown in Figure 60 (page 110). ...
Page 108
... Rev CK# CK WRITE NOP Bank a, Col b WL ± t DQSS DQSS DQSS 108 1Gb: x4, x8, x16 DDR2 SDRAM T2 T2n T3 T3n T4 NOP NOP NOP DQSS DQSS Transitioning Data Don’t Care t DQSS. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 109
... CCD Bank, Bank, Col b Col ± DQSS CK# CK WRITE NOP NOP Bank, Col b WL ± t DQSS 109 1Gb: x4, x8, x16 DDR2 SDRAM T2n T3 T3n T4 T4n T5 T5n NOP NOP NOP Transitioning Data t DQSS. T2n T3 T3n T4 T4n T5 T5n WRITE NOP NOP Bank, Col n 1 ...
Page 110
... NOP 2 Valid 5 Valid issued to banks used for WRITEs at T0 and T2. starts with T7 and not T5 (because from MR and not the truncated length and T2 can be either same bank or different bank). terrupting WRITE command. 110 1Gb: x4, x8, x16 DDR2 SDRAM NOP 2 NOP 2 Valid 4 Valid ...
Page 111
... WTR is required for any READ following a WRITE to the same device, but it is not re- quired between module ranks. t WTR is referenced from the first positive CK edge after the last data-in pair. greater. 111 1Gb: x4, x8, x16 DDR2 SDRAM NOP READ NOP NOP ...
Page 112
... referenced from the first positive CK edge after the last data-in pair. and WRITE commands may be to different banks, in which case the PRECHARGE command could be applied earlier. 112 1Gb: x4, x8, x16 DDR2 SDRAM NOP NOP NOP t WR Transitioning Data t DQSS not required and Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ ...
Page 113
... Bank x t RCD ± t DQSS (NOM) these times DSH is applicable during DQSS (MIN) and is referenced from T6 DSS is applicable during DQSS (MAX) and is referenced from T7. 113 1Gb: x4, x8, x16 DDR2 SDRAM T5 T5n T6 T6n T7 T8 NOP 1 NOP 1 NOP 1 NOP RAS 5 t DQSL t DQSH t WPST ...
Page 114
... WL ± t DQSS (NOM) t WPRE these times. rounding up to the next integer value. der DSH is applicable during DQSS (MIN) and is referenced from T6 DSS is applicable during DQSS (MAX) and is referenced from T7. 114 1Gb: x4, x8, x16 DDR2 SDRAM T5 T5n T6 T6n T7 T8 NOP 1 NOP 1 NOP 1 NOP RAS 5 ...
Page 115
... WR starts at the end of the data burst regardless of the data mask condition DSH is applicable during DQSS (MIN) and is referenced from T7 DSS is applicable during DQSS (MAX) and is referenced from T8. 115 1Gb: x4, x8, x16 DDR2 SDRAM T9 T6 T6n T7 T7n T8 NOP 1 NOP 1 NOP RAS ...
Page 116
... DSH (MIN) generally occurs during t DSS (MIN) generally occurs during t RP timing applies. When the PRECHARGE (ALL) com- t RPA timing applies, regardless of the number of banks opened. 116 1Gb: x4, x8, x16 DDR2 SDRAM T3 T3n T4 t DSS 2 t DSH 1 t DSS DQSL t DQSH ...
Page 117
... REFRESH The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in- terval of 7.8125μs (MAX) and all rows in all banks must be refreshed at least once every 64ms. The refresh period begins when the REFRESH command is registered and ends t RFC (MIN) later. The average interval must be reduced to 3.9μs (MAX) when T 85° ...
Page 118
... First, the differential clock must be stable and meet prior to CKE going back to HIGH. Once CKE is HIGH ( with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com- mands issued for ments is used to apply NOP or DESELECT commands for 200 clock cycles before apply- ing any other command ...
Page 119
... XSNR is required before any nonREAD command can be applied. off ( TT tering self refresh at state T1. t XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0. fresh. 119 1Gb: x4, x8, x16 DDR2 SDRAM Tb0 Tc0 Ta2 t ISXR 2 t CKE 3 NOP 4 NOP 4 Valid 5 ...
Page 120
... Figure 70 (page 123)–Figure 77 (page 126). Table 44 (page 122) is the CKE Truth Table. DDR2 SDRAM requires CKE to be registered HIGH (active) at all times that an access is in progress—from the issuing of a READ or WRITE command until completion of the burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined when the read postamble is satisfied ...
Page 121
... XARDS timing is used for exit active power-down to READ command if slow exit is se- lected via MR (bit 12 = 1). the DLL was not in a locked state when CKE went LOW, the DLL must be reset after exit- ing power-down mode for proper READ operation. 121 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode ...
Page 122
... CKE (n) is the logic state of CKE at clock edge n; CKE ( was the state of CKE at the Notes: 2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n. 3. Command (n) is the command registered at clock edge n, and action ( result of 4. The state of ODT does not affect the states described in this table. The ODT function is 5. Power-down modes do not perform any REFRESH operations. The duration of power- 6. “ ...
Page 123
... Power-down or self refresh entry may occur after the READ burst completes. PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev NOP NOP Valid entry NOP NOP entry is at T6. 123 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode NOP 1 Valid DO DO Power-down 2 or self refresh entry Transitioning Data NOP 1 Valid Valid DO DO ...
Page 124
... NOP NOP Valid cur later at Ta1, prior to RP being satisfied next integer CK. 124 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode NOP 1 Valid Valid t WTR Power-down or self refresh entry 1 Transitioning Data T5 Ta0 Ta1 Valid 1 Valid NOP WR 2 Power-down or self refresh entry Indicates a break in ...
Page 125
... REFRESH REFRESH command. Precharge power-down entry occurs prior to fied Valid ACT VALID VATE command. Active power-down entry occurs prior to 125 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode T2 T3 NOP t CKE (MIN) Power-down 1 entry Don’t Care t RFC (MIN) being satis NOP ...
Page 126
... PRE Valid All banks A10 vs Single bank CKE 1 x PRECHARGE command. Precharge power-down entry occurs prior to isfied Valid LM Valid 126 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode T2 T3 NOP t CKE (MIN Power-down 1 entry Don’t Care NOP NOP t CKE (MIN) t MRD ...
Page 127
... Precharge Power-Down Clock Frequency Change When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off and CKE must logic LOW level. A minimum of two differential clock cycles must pass after CKE goes LOW before clock frequency may change. The device input clock frequency is allowed to change only within minimum and maximum operating fre- quencies specified for the particular speed grade ...
Page 128
... If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be- fore CKE is raised HIGH, at which time the normal initialization sequence must occur (see Initialization) ...
Page 129
... V , and V must be valid at all times. DD DDL DDQ TT REF represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri- ate configuration (x4, x8, x16). completion of the burst. 129 1Gb: x4, x8, x16 DDR2 SDRAM T5 Ta0 CKE (MIN) 1 NOP 2 High-Z High-Z ...
Page 130
... AXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0 AXPD (MIN) is not satisfied, AOFPD timing parameters apply. t AXPD (MIN) is satisfied, 130 1Gb: x4, x8, x16 DDR2 SDRAM t AOF timing parameters are applied, as shown in t AOFPD timing parameters apply. t ANPD (MIN AONPD timing parameters apply. ...
Page 131
... Active power-down slow (asynchronous) Precharge power-down (asynchronous AOND/ AOFD (synchronous AONPD/ AOFPD (asynchronous) 131 1Gb: x4, x8, x16 DDR2 SDRAM Synchronous t t AXPD (8 CKs) First CKE latched HIGH Any mode except self refresh mode t AOND/ Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 132
... MOD window until Valid Valid Valid Valid Valid Valid t AOND TT t AON (MIN) t AON (MAX) 132 1Gb: x4, x8, x16 DDR2 SDRAM t MOD (MAX) updates the R setting. TT Ta2 Ta3 Ta4 NOP NOP NOP 2 t MOD t IS Undefined New setting Indicates a break in time scale t MOD is met ...
Page 133
... Valid Valid Valid Valid Valid Valid t AONPD (MAX) t AONPD (MIN) t AOFPD (MIN) Transitioning NOP NOP NOP TT TT Transitioning R TT 133 1Gb: x4, x8, x16 DDR2 SDRAM Valid Valid Valid Valid Valid Valid Valid Valid t AOFPD (MAX) R Unknown NOP NOP NOP t ANPD (MIN) ...
Page 134
... CK# CK Command CKE ODT R ODT R PDF: 09005aef821ae8bf 1GbDDR2.pdf – Rev NOP NOP NOP TT TT Transitioning R TT 134 1Gb: x4, x8, x16 DDR2 SDRAM NOP NOP NOP NOP t ANPD (MIN) t AOND t AON (MAX) t AON (MIN) t AONPD (MAX) t AONPD (MIN) R Unknown Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 135
... Rev Ta0 NOP NOP NOP NOP t AXPD (MIN) Indicates a break in R Unknown TT time scale 135 1Gb: x4, x8, x16 DDR2 SDRAM Ta1 Ta2 Ta3 Ta4 NOP NOP NOP NOP t AOFD t AOF (MAX) t AOF (MIN) t AOFPD (MAX) t AOFPD (MIN Transitioning R ...
Page 136
... Rev Ta0 NOP NOP NOP NOP t AXPD (MIN) Indicates a break time scale times occur. 136 1Gb: x4, x8, x16 DDR2 SDRAM Ta1 Ta2 Ta3 Ta4 NOP NOP NOP NOP t AOND t AON (MAX) t AON (MIN) t AONPD (MAX) t AONPD (MIN) Unknown R ...