MT47H128M8HQ-187EIT:G Micron Technology Inc, MT47H128M8HQ-187EIT:G Datasheet - Page 101

• Manufacturer Part Number: MT47H128M8HQ-187EIT:G
• Manufacturer: Micron Technology Inc

Specifications of MT47H128M8HQ-187EIT:G

• Lead Free Status / Rohs Status: Compliant

READ with Auto Precharge
Table 42: READ Using Concurrent Auto Precharge
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
From Command (Bank n)
READ with auto precharge
If A10 is high when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock
edge that is AL + (BL/2) cycles later than the read with auto precharge command provi-
ded
edge, the start point of the auto precharge operation will be delayed until
satisfied. If
to precharge operation will be delayed until
precharge is pushed out by
happens (not at the next rising clock edge after this event).
When BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE
command is AL + (
auto precharge to the next ACTIVATE command is AL + 2 clocks + (
term (
tion can also be used: AL + BL/2 - 2CK + (
charge does not start earlier than two clocks after the last 4-bit prefetch.
READ with auto precharge command may be applied to one bank while another bank is
operational. This is referred to as concurrent auto precharge operation, as noted in Ta-
ble 42. Examples of READ with precharge and READ with auto precharge with applica-
ble timing requirements are shown in Figure 52 (page 102) and Figure 53 (page 103),
respectively.
t
WRITE or WRITE with auto precharge
RAS (MIN) and
READ or READ with auto precharge
t
RTP +
PRECHARGE or ACTIVATE
To Command (Bank m)
t
RTP (MIN) is not satisfied at this rising clock edge, the start point of the au-
t
RP)/
t
t
CK is always rounded up to the next integer. A general purpose equa-
RTP +
t
RTP are satisfied. If
t
RP)/
t
RTP ,
101
t
CK. When BL = 8, the minimum time from READ with
t
RP starts at the point where the internal precharge
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
RAS (MIN) is not satisfied at this rising clock
RTP +
(with Concurrent Auto Precharge)
t
RTP (MIN) is satisfied. When the internal
1Gb: x4, x8, x16 DDR2 SDRAM
t
RP)/
t
Minimum Delay
CK. In any event, the internal pre-
(BL/2) + 2
BL/2
1
‹ 2007 Micron Technology, Inc. All rights reserved.
t
RTP +
t
t
RAS (MIN) is
RP)/
t
CK. The
READ
Units
t
t
t
CK
CK
CK