MT47H128M8HQ-187EIT:G Micron Technology Inc, MT47H128M8HQ-187EIT:G Datasheet - Page 81

• Manufacturer Part Number: MT47H128M8HQ-187EIT:G
• Manufacturer: Micron Technology Inc

Specifications of MT47H128M8HQ-187EIT:G

• Lead Free Status / Rohs Status: Compliant

Burst Type
Table 41: Burst Definition
Operating Mode
DLL RESET
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
Burst Length
4
8
Starting Column Address
Accesses within a given burst may be programmed to be either sequential or inter-
leaved. The burst type is selected via bit M3, as shown in Figure 35. The ordering of ac-
cesses within a burst is determined by the burst length, the burst type, and the starting
column address, as shown in Table 41. DDR2 SDRAM supports 4-bit burst mode and 8-
bit burst mode only. For 8-bit burst mode, full interleaved address ordering is suppor-
ted; however, sequential address ordering is nibble-based.
The normal operating mode is selected by issuing a command with bit M7 set to “0,”
and all other bits set to the desired values, as shown in Figure 35 (page 80). When bit M7
is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1”
places the DDR2 SDRAM into a test mode that is only used by the manufacturer and
should not be used. No operation or functionality is guaranteed if M7 bit is “1.”
DLL RESET is defined by bit M8, as shown in Figure 35. Programming bit M8 to “1” will
activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a
value of “0” after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ
command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of
the
(A2, A1, A0)
t
AC or
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0
0 1
1 0
1 1
t
DQSCK parameters.
Burst Type = Sequential
81
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
Order of Accesses Within a Burst
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
Burst Type = Interleaved
Mode Register (MR)
‹ 2007 Micron Technology, Inc. All rights reserved.
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0