MAX503CAG+T Maxim Integrated Products, MAX503CAG+T Datasheet - Page 11

• Manufacturer Part Number: MAX503CAG+T
• Description: IC DAC 10BIT 5V LP 24-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX503CAG+T

• Settling Time: 25µs
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 640mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4. MAX503 Write-Cycle Timing Diagram
A small error voltage is added to the reference output
by the reference current flowing through the N-channel
pull-down transistor. The switch’s on resistance should
be less than 5Ω. A typical reference current of 100µA
would add 0.5mV to REFOUT. Since the reference cur-
rent and on resistance increase with temperature, the
overall temperature coefficient will degrade slightly.
As data is loaded into the DAC and the output moves
above GND, the op-amp quiescent current increases to
its nominal value and the total operating current aver-
ages 250µA. Using dual supplies (±5V), the op amp is
fully biased continuously, and the V
more constant at 250µA. The V
150µA.
The MAX503 logic inputs are compatible with TTL and
CMOS logic levels. However, to achieve the lowest
power dissipation, drive the digital inputs with rail-to-rail
CMOS logic. With TTL logic levels, the power require-
ment increases by a factor of approximately 2.
OR 4-BIT NIBBLE)
(8-BIT BYTE
DATA BITS
A0–A1
LDAC
CLR
WR
CS
NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS
______________________________________________________________________________________
t
CLR
SS
DD
current is typically
supply current is
5V, Low-Power, Parallel-Input,
V
V
IH
IL
V
IH +
t
AWS
2
V
Voltage-Output, 10-Bit DAC
IL
t
ADDRESS BUS VALID
CWS
In order to provide hardware and software compatibility
with the 12-bit MAX530, the MAX503 employs a 12-bit
digital interface. As shown in Figure 3, there is actually
a 12-bit input latch, and therefore 12 bits of data should
be written. The two least significant bits (S1 and S0) are
sub-LSB, and must always be 0s. Designed to interface
with 4-bit, 8-bit, and 16-bit microprocessors (µPs), the
MAX503 uses 8 data pins and double-buffered logic
inputs to load data as 4 + 4 + 4 or 8 + 4. The 12-bit
DAC latch is updated simultaneously through the con-
trol signal LDAC. Signals A0, A1, WR, and CS select
which input latches to update. The 12-bit data is bro-
ken down into nibbles (NB); NBL is the enable signal
for the lowest 4 bits (S0, S1, D0, D1), NBM is the
enable for the middle 4 bits, and NBH is the enable for
the highest and most significant 4 bits. Table 2 lists the
address decoding scheme.
Refer to Figure 4 for the MAX503 write-cycle timing
diagram.
t
WR
V
V
IH
IL
t
DS
DATA BUS
VALID
t
AWH
t
DH
t
CWH
Parallel Logic Interface
t
LDAC
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