EPM7064LI44-15 Altera, EPM7064LI44-15 Datasheet - Page 42

• Manufacturer Part Number: EPM7064LI44-15
• Description: IC MAX 7000 CPLD 64 44-PLCC
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7064LI44-15

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1250
• Number Of I /o: 36
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 4
• Family Name: MAX 7000
• # Macrocells: 64
• Number Of Usable Gates: 1250
• Frequency (max): 100MHz
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 36
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1784

MAX 7000 Programmable Logic Device Family Data Sheet
42
Symbol
t
t
t
t
t
t
f
t
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 29. EPM7064S External Timing Parameters (Part 2 of 2)
Table 30. EPM7064S Internal Timing Parameters (Part 1 of 2)
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Output data hold time after
clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Output buffer and pad delay
Output buffer and pad delay
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
Register hold time
Parameter
Parameter
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
C1 = 35 pF
(2)
C1 = 35 pF
(4)
(4)
(5)
Conditions
Conditions
(6)
(6)
(3)
Min Max Min Max Min Max Min Max
175.4
175.4
250.0
Min Max Min Max Min Max Min Max
2.5
2.5
1.0
2.5
0.8
1.7
-5
-5
5.4
5.7
5.7
0.2
0.2
2.2
3.1
0.9
2.6
2.5
0.7
0.2
0.7
5.2
4.0
4.5
9.0
4.0
140.8
140.8
200.0
2.5
2.5
2.5
1.0
1.0
2.0
Note (1)
Note (1)
-6
-6
Speed Grade
Speed Grade
6.7
7.1
7.1
0.2
0.2
3.8
3.2
3.2
0.8
0.3
0.8
5.3
4.0
4.5
9.0
2.6
1.1
4.0
125.0
125.0
166.7
3.0
3.0
3.0
1.0
3.0
2.0
-7
-7
7.5
8.0
8.0
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
2.5
7.0
4.0
4.5
9.0
4.0
Altera Corporation
100.0
100.0
125.0
4.0
4.0
4.0
1.0
2.0
3.0
-10
-10
10.0
10.0
10.0
0.5
0.5
5.0
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
1.0
0.8
Unit
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns