EPM2210F256I5N Altera, EPM2210F256I5N Datasheet - Page 24

• Manufacturer Part Number: EPM2210F256I5N
• Description: IC MAX II CPLD 2210 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM2210F256I5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of I /o: 204
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 2210
• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 204
• Propagation Delay: 11.2ns
• Global Clock Setup Time: 1.2ns
• Frequency: 304MHz
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 544-2268

2–16
Table 2–2. MAX II Device Routing Scheme
Global Signals
MAX II Device Handbook
LUT Chain
Register Chain
Local
Interconnect
DirectLink
Interconnect
R4 Interconnect
C4 Interconnect
LE
UFM Block
Column IOE
Row IOE
Note to
(1) These categories are interconnects.
Source
Table
2–2:
Chain
LUT
v
—
—
—
—
—
—
—
—
—
The UFM block communicates with the logic array similar to LAB-to-LAB interfaces.
The UFM block connects to row and column interconnects and has local interconnect
regions driven by row and column interconnects. This block also has DirectLink
interconnects for fast connections to and from a neighboring LAB. For more
information about the UFM interface to the logic array, see
Block” on page
Table 2–2
Each MAX II device has four dual-purpose dedicated clock pins (GCLK[3..0], two
pins on the left side and two pins on the right side) that drive the global clock network
for clocking, as shown in
purpose I/O if they are not used to drive the global clock network.
The four global clock lines in the global clock network drive throughout the entire
device. The global clock network can provide clocks for all resources within the
device including LEs, LAB local interconnect, IOEs, and the UFM block. The global
clock lines can also be used for global control signals, such as clock enables,
synchronous or asynchronous clears, presets, output enables, or protocol control
signals such as TRDY and IRDY for PCI. Internal logic can drive the global clock
network for internally-generated global clocks and control signals.
the various sources that drive the global clock network.
Register
Chain
v
—
—
—
—
—
—
—
—
—
shows the MAX II device routing scheme.
Local
2–18.
(1)
—
—
v
v
v
v
v
—
—
—
DirectLink
Figure
(1)
v
v
v
—
—
—
—
—
—
—
2–13. These four pins can also be used as general-
R4
—
—
—
—
v
v
v
v
—
v
(1)
Destination
C4
v
v
v
v
v
v
—
—
—
—
(1)
v
v
v
—
—
—
—
—
—
—
LE
“User Flash Memory
Block
© October 2008 Altera Corporation
UFM
v
—
—
—
—
—
—
—
—
—
Chapter 2: MAX II Architecture
Figure 2–13
Column
IOE
v
v
—
—
—
—
—
—
—
—
Global Signals
Row
IOE
v
—
—
v
—
—
—
—
—
—
shows
Fast I/O
(1)
—
—
—
—
—
—
v
—
—
—