EPM3512AFI256-10N Altera, EPM3512AFI256-10N Datasheet - Page 17

• Manufacturer Part Number: EPM3512AFI256-10N
• Description: IC MAX 3000A CPLD 512 256-FBGA
• Manufacturer: Altera
• Series: MAX® 3000Ar

Specifications of EPM3512AFI256-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 32
• Number Of Macrocells: 512
• Number Of Gates: 10000
• Number Of I /o: 208
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 32
• Family Name: MAX 3000A
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 208
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Programming
with External
Hardware
IEEE Std.
1149.1 (JTAG)
Boundary–Scan
Support
Altera Corporation
SAMPLE/PRELOAD
EXTEST
BYPASS
IDCODE
USERCODE
ISP Instructions
Table 7. MAX 3000A JTAG Instructions
JTAG Instruction
f
f
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins
Allows the external circuitry and board–level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins
Places the 1–bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO
Selects the 32–bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO
These instructions are used when programming MAX 3000A devices via the JTAG ports
with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL
file, JBC file, or SVF file via an embedded processor or test equipment
MAX 3000A devices can be programmed on Windows–based PCs with an
Altera Logic Programmer card, MPU, and the appropriate device adapter.
The MPU performs continuity checking to ensure adequate electrical
contact between the adapter and the device.
For more information, see the
The Altera software can use text– or waveform–format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera devices.
For more information, see
MAX 3000A devices include the JTAG BST circuitry defined by IEEE
Std. 1149.1–1990.
MAX 3000A devices. The pin-out tables found on the Altera web site
(http://www.altera.com) or the Altera Digital Library show the location of
the JTAG control pins for each device. If the JTAG interface is not
required, the JTAG pins are available as user I/O pins.
MAX 3000A Programmable Logic Device Family Data Sheet
Table 7
describes the JTAG instructions supported by
Programming Hardware
Description
Altera Programming Hardware Data
Manufacturers.
Sheet.
17