EPM7256SQC208-10N Altera, EPM7256SQC208-10N Datasheet - Page 47

• Manufacturer Part Number: EPM7256SQC208-10N
• Description: IC MAX 7000 CPLD 256 208-PQFP
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7256SQC208-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 164
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Family Name: MAX 7000S
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 164
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
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Symbol
Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
ACNT
ACNT
MAX
Table 33. EPM7160S External Timing Parameters (Part 2 of 2)
Table 34. EPM7160S Internal Timing Parameters (Part 1 of 2)
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Output buffer and pad delay
Output buffer and pad delay
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast
input
Register hold time of fast
input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Parameter
Parameter
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
(4)
(5)
Conditions
Conditions
(6)
(6)
MAX 7000 Programmable Logic Device Family Data Sheet
149.3
166.7
Min Max Min Max Min Max Min Max
Min Max Min Max Min Max Min Max
1.0
1.6
1.9
0.6
-6
-6
6.7
0.2
0.2
2.8
2.8
0.7
0.4
0.9
4.0
4.5
9.0
1.3
2.0
2.6
3.6
1.0
5.4
4.0
1.0
2.9
2.8
2.4
122.0
166.7
1.2
2.0
2.2
0.8
Note (1)
Note (1)
-7
-7
Speed Grade
Speed Grade
8.2
0.3
0.3
3.2
4.3
1.3
3.4
3.4
0.9
0.5
1.0
5.5
4.0
4.5
9.0
4.0
1.6
1.3
3.5
3.4
2.4
3.0
100.0
125.0
2.0
3.0
3.0
0.5
-10
-10
10.0
0.5
0.5
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
2.0
5.0
1.0
1.0
5.0
0.8
9.0
5.0
2.0
5.0
3.0
100.0
76.9
4.0
4.0
2.0
1.0
-15
-15
13.0
10.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
8.0
6.0
7.0
6.0
1.0
1.0
6.0
6.0
1.0
4.0
Unit
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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