EPM7512BFC256-7 Altera, EPM7512BFC256-7 Datasheet - Page 23

• Manufacturer Part Number: EPM7512BFC256-7
• Description: IC MAX 7000 CPLD 512 256-FBGA
• Manufacturer: Altera
• Series: MAX® 7000Br

Specifications of EPM7512BFC256-7

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 2.375 V ~ 2.625 V
• Number Of Logic Elements/blocks: 32
• Number Of Macrocells: 512
• Number Of Gates: 10000
• Number Of I /o: 212
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Altera Corporation
Table 10. MAX 7000B MultiVolt I/O Support
V
CCIO
1.8
2.5
3.3
(V)
1.8
v
v
v
Open-Drain Output Option
MAX 7000B devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. It can
also provide an additional wired-OR plane.
Programmable Ground Pins
Each unused I/O pin on MAX 7000B devices may be used as an additional
ground pin. This programmable ground feature does not require the use
of the associated macrocell; therefore, the buried macrocell is still
available for user logic.
Slew-Rate Control
The output buffer for each MAX 7000B I/O pin has an adjustable output
slew rate that can be configured for low-noise or high-speed performance.
A faster slew rate provides high-speed transitions for high-performance
systems. However, these fast transitions may introduce noise transients
into the system. A slow slew rate reduces system noise, but adds a
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the
slew rate is set for low-noise performance. Each I/O pin has an individual
EEPROM bit that controls the slew rate, allowing designers to specify the
slew rate on a pin-by-pin basis. The slew rate control affects both the rising
and falling edges of the output signal.
Advanced I/O Standard Support
The MAX 7000B I/O pins support the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, GTL+, SSTL-3 Class I and II, and SSTL-2
Class I and II.
Input Signal (V)
2.5
v
v
v
3.3
v
v
v
MAX 7000B Programmable Logic Device Data Sheet
5.0
1.8
v
Output Signal (V)
2.5
v
3.3
v
5.0
v
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