Z8937320FSG Zilog, Z8937320FSG Datasheet - Page 34

• Manufacturer Part Number: Z8937320FSG
• Description: DSP 20MHZ 80-PQFP
• Manufacturer: Zilog
• Series: Z893x3r
• Type: Fixed Pointr

Specifications of Z8937320FSG

• Interface: SPI, 3-Wire Serial
• Clock Rate: 20MHz
• Non-volatile Memory: OTP (16 kB)
• On-chip Ram: 1kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O PORTS (Continued)
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
Port0Ñ16-Bit Programmable I/O
Bank15/EXT0 is the Port0 direction control register.
Bank15/EXT1 includes specific bits to enable and config-
ure Port0. The Port0 data register is Ext4 in Banks 0, 1, or 5.
34
Bank 15/EXT1
D15 D14 D13 D12 D11 D10 D9
Bank 15/Ext 0 Reg
D15 D14 D13 D12 D11 D10 D9
D8
Figure 25. Port 0 Control Register
Figure 26. Bank15/EXT1 Register
D7
D6
D8
D5 D4 D3
D7
D6
D5
D2 D1 D0
D4
D3
D2 D1 D0
Allocation of External Data (ED) Bus/Port0 Pins
INT2
0 = Disabled (default)
1 = Enabled
INT1
0 = Disabled (default)
1 = Enabled
CLKOUT
0 = Disabled (default)
1 = Enabled
Port1 Outputs
0 = Push-Pull (default)
1 = Open-Drain
Port0 Outputs
0 = Push-Pull (default)
1 = Open-Drain
Port I/O Output Bit Directions
0 = Input (default)
1 = Output
000 = ED Bus 15-0 (default)
001 = Pins 15–8
010 = Reserved
011 = Pins 15–8
100 = P0.15–P0.0
101 = Pins 15–8
110 = Reserved
111 = Reserved
Pins 7–0
Pins 7–0
Pins 7–0
Port I/O Direction
0 = Input (default)
1 = Output
ED Bus 7–0
ED Bus 7–0
P0.7–P0.0
P1.7–P1.0,
P0.15–P08,
P1.7–P1.0
DS000202-DSP0599
ZiLOG