DSPB56720AG Freescale Semiconductor, DSPB56720AG Datasheet - Page 36

• Manufacturer Part Number: DSPB56720AG
• Description: AUDIO PROCESSOR SYMPH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56720AG

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: External
• On-chip Ram: 744kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP567xx
• Core: 56300
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 200 MIPs
• Maximum Clock Frequency: 200 MHz
• Operating Supply Voltage: 1 V, 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Operating Supply Voltage (typ): 1/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Maximum Speed: 200 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

36
No.
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
Write data strobe assertion width 7
HACK write assertion width
Write data strobe deassertion width 7
HACK write deassertion width
HAS assertion width
HAS deassertion to data strobe assertion 8
Host data input setup time before write data strobe deassertion 7
Host data input setup time before HACK write deassertion
Host data input hold time after write data strobe deassertion 7
Host data input hold time after HACK write deassertion
Read data strobe assertion to output data active from high impedance 3
HACK read assertion to output data active from high impedance
Read data strobe assertion to output data valid 3
HACK read assertion to output data valid
Read data strobe deassertion to output data high impedance 3
HACK read deassertion to output data high impedance
Output data hold time after read data strobe deassertion
Output data hold time after HACK read deassertion
HCS assertion to read data strobe deassertion
HCS assertion to write data strobe deassertion
HCS assertion to output data valid
HCS hold time after data strobe deassertion 8
Address (AD7—AD0) setup time before HAS deassertion (HMUX=1)
Address (AD7—AD0) hold time after HAS deassertion (HMUX=1)
A10—A8 (HMUX=1), A2—A0 (HMUX=0), HR/W setup time before data
strobe assertion 8
A10—A8 (HMUX=1), A2—A0 (HMUX=0), HR/W hold time after data
strobe deassertion 8
Delay from read data strobe deassertion to
host request assertion for “Last Data Register” read 3, 4, 9
• after ICR, CVR and “Last Data Register” writes 4
• after IVR writes, or
• after TXH:TXM writes (with HBE=0), or
• after TXL:TXM writes (with HBE=1)
• Read
• Write
Symphony
Table 15. HDI24 Timing Parameters (Continued)
Characteristics 2
™
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
3
7
3
Expression
2 × T
T
C
T
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+ 9.9
C
C
+ 6.6
Freescale Semiconductor
13.2
16.6
16.5
14.9
Min
9.9
0.0
9.9
3.3
5.9
3.3
9.9
0.0
4.7
3.3
4.7
3.3
5.0
—
—
—
0
200 MHz
Max
29.6
19.1
9.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—