DSPB56721AG Freescale Semiconductor, DSPB56721AG Datasheet - Page 37

• Manufacturer Part Number: DSPB56721AG
• Description: AUDIO PROCESSOR SYMPH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56721AG

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: External
• On-chip Ram: 744kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Notes:
1. In the timing diagrams that follow, the controls pins are drawn as active low. The pin polarity is programmable.
2. V
3. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
4. The “last data register” is the register at address $7, which is the last location to be read or written in data transfers.
5. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers
6. This timing is applicable only if two consecutive reads from one of these registers are executed.
7. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
8. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the
9. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.
10. In this calculation, the host request signal is pulled up by a 4.7 kW resistor in the open-drain mode.
11. HDI24_1 specs match those of HDI24.
No.
339
340
341
342
343
344
without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
single data strobe mode.
CC
Delay from write data strobe deassertion to
host request assertion for “Last Data Register” write 4, 7, 9
Delay from data strobe assertion to
host request deassertion for “Last Data Register” read or write (HROD =
0) 4, 8, 9
Delay from data strobe assertion to
host request deassertion for “Last Data Register” read or write (HROD =
1, open drain Host Request) 4, 8, 9, 10
Delay from DMA HACK deassertion to HOREQ assertion
Delay from DMA HACK assertion to HOREQ deassertion
Delay from DMA HACK assertion to HOREQ deassertion for “Last Data
Register” read or write
= 1.0 V ± 10%; T
• For “Last Data Register” read 4
• For “Last Data Register” write 4
• For other cases
• HROD = 0
• HROD = 1, open drain Host Request 4, 10
4
Symphony
J
= —40°C to +100°C; C
Table 15. HDI24 Timing Parameters (Continued)
Characteristics 2
™
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
L
= 50 pF.
2 × T
1 × T
Expression
2 × T
C
C
—
—
—
—
—
+ 19.1
+ 19.1
C
10.0
29.1
24.1
Min
0.0
—
—
—
—
200 MHz
300.0
300.0
Max
19.1
20.2
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
37