MSC8113TMP4800V Freescale Semiconductor, MSC8113TMP4800V Datasheet - Page 20

• Manufacturer Part Number: MSC8113TMP4800V
• Description: DSP TRI-CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8113TMP4800V

• Interface: Ethernet, I²C, TDM, UART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Characteristics
2.5.4.2
The MSC8113 has two mechanisms for writing the reset configuration:
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on
Configuration Mode and boot and operating conditions:
2.5.4.3
Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or
through the system bus.
20
Note:
No.
1
2
3
5
6
7
8
•
•
•
•
•
•
•
•
•
•
Through the direct slave interface (DSI)
Through the system bus. When the reset configuration is written through the system bus, the MSC8113 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configuration word is applied.
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
Required external PORESET duration minimum
•
•
•
Delay from deassertion of external PORESET to deassertion of internal
PORESET
•
Delay from de-assertion of internal PORESET to SPLL lock
•
•
•
Delay from SPLL to HRESET deassertion
•
Delay from SPLL lock to SRESET deassertion
•
Setup time from assertion of
CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of
PORESET
Hold time from deassertion of PORESET to deassertion of
CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and
MODCK[1–2]
Timings are not tested, but are guaranteed by design.
CLKIN = 20 MHz
CLKIN = 100 MHz (300 MHz core)
CLKIN = 133 MHz (400 MHz core)
CLKIN = 20 MHz to 133 MHz
CLKIN = 20 MHz (RDF = 1)
CLKIN = 100 MHz (RDF = 1) (300 MHz core)
CLKIN = 133 MHz (RDF = 2) (400 MHz core)
REFCLK = 40 MHz to 133 MHz
REFCLK = 40 MHz to 133 MHz
Table 12. Timing for a Reset Configuration Write through the DSI or System Bus
Reset Configuration
Reset Timing Tables
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Characteristics
RSTCONF
, CNFGS, DSISYNC, DSI64,
RSTCONF
,
clock-division factor)
6400/(CLKIN/RDF)
(PLL reference
Expression
512/REFCLK
515/REFCLK
1024/CLKIN
16/CLKIN
PORESET
deassertion to define the Reset
Freescale Semiconductor
6.17
3.08
3.10
Min
800
160
120
320
64
96
3
5
12.88
Max
51.2
12.8
320
64
96
—
—
—
—
—
Unit
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns