ADMCF341BR Analog Devices Inc, ADMCF341BR Datasheet - Page 33

IC DSP 3CH 12BIT MOT-CTRL 28SOIC

ADMCF341BR

Manufacturer Part Number
ADMCF341BR
Description
IC DSP 3CH 12BIT MOT-CTRL 28SOIC
Manufacturer
Analog Devices Inc
Series
Motor Controlr
Type
Motor Controlr
Datasheet

Specifications of ADMCF341BR

Rohs Status
RoHS non-compliant
Interface
Synchronous Serial Port (SSP)
Clock Rate
20MHz
Non-volatile Memory
FLASH (12 kB), ROM (12kB)
On-chip Ram
2.5kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADMCF341BRZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.
REV. B
1 = INDEPENDENT MODE
0 = OFFSET MODE
1 = CLKOUT RATE
0 = SPORT MODE
1 = UART MODE
0 = CLKIN RATE
0 = STANDARD
1 = SPI MODE
1 = VOLTAGE
1 = VOLTAGE
1 = VOLTAGE
1 = REVERSE
0 = SPORT
0 = I
0 = I
0 = I
0 = PHA0
1 = PHA1
SENSE
SENSE
SENSE
0 = 1ST HALF OF PWM
1 = 2ND HALF OF PWM
MODE SELECT
MODE SELECT
CYCLE
CYCLE
CHANNEL 3
SELECTION
CHANNEL 2
SELECTION
CHANNEL 1
SELECTION
SPI CLOCK
SPI CLOCK
POLARITY
SPI MODE
COUNTER
AUX PWM
SPORT 0
SPORT 0
PHASE
15
15
15
ADC
0
0
0
14
14
14
0
0
0
Figure 29. Configuration of Status/Control Registers
15
0
13
13
13
0
0
0
14
0
12
12
12
0
0
0
13
PWM TIMER
0
11
11
11
0
STATUS
0
0
12
0
10
10
10
0
0
0
11
0
9
0
0
WDTIMER (W)
9
0
9
SYSSTAT (R)
IRQFLAG (R)
10
0
8
0
8
8
0
0
MODECTRL (R/W)
0
9
7
0
0
0
7
7
–33–
8
0
6
0
6
0
6
0
7
0
5
0
5
0
5
0
6
0
0
0
4
4
4
0
5
0
3
0
3
0
3
0
4
2
1
2
0
2
0
3
0
0
1
1
1
0
2
0
0
0
0
0
0
1
0
PIN STATUS
WATCHDOG
DM (0x2016)
DM (0x2018)
PWMTRIP
PWMTRIP INTERRUPT
PWMSYNC INTERRUPT
DM (0x2017)
STATUS
PWMTRIP
ADC MUX
CONTROL
INTERRUPT
PWMSYNC
INTERRUPT
SPORT1 MODE
SELECT
PWM UPDATE
MODE SELECT
0
0
DM (0x2015)
ADC MUX CONTROL
00 VAUX0
01 VAUX1
10 VAUX2
11 VREF
0 = LOW
1 = HIGH
0 = NORMAL
1 = WATCHDOG RESET
OCCURRED
ADMC(F)341
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = SINGLE UPDATE MODE
1 = DOUBLE UPDATE MODE
0 = BOOT MODE
1 = UART MODE
NOT USED IN ADMCF341
SET BIT TO ZERO
0 = NO INTERRUPT
1 = INTERRUPT
OCCURRED

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