ADSP-2185MKST-300 Analog Devices Inc, ADSP-2185MKST-300 Datasheet - Page 24

IC DSP CONTROLLER 16BIT 100LQFP

ADSP-2185MKST-300

Manufacturer Part Number
ADSP-2185MKST-300
Description
IC DSP CONTROLLER 16BIT 100LQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet

Specifications of ADSP-2185MKST-300

Rohs Status
RoHS non-compliant
Interface
Host Interface, Serial Port
Clock Rate
75MHz
Non-volatile Memory
External
On-chip Ram
80kB
Voltage - I/o
3.30V
Voltage - Core
2.50V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Device Core Size
16b
Architecture
Enhanced Harvard
Format
Fixed Point
Clock Freq (max)
75MHz
Mips
75
Device Input Clock Speed
75MHz
Ram Size
80KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (min)
2.37V
Operating Supply Voltage (max)
2.63/3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-2185MKST-300
Manufacturer:
ADI
Quantity:
300
Part Number:
ADSP-2185MKST-300
Manufacturer:
ADI
Quantity:
451
Part Number:
ADSP-2185MKST-300
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Parameter
Interrupts and Flags
Timing Requirements:
t
t
Switching Characteristics:
t
t
NOTES
1
2
3
4
5
ADSP-2185M
If IRQx and FI inputs meet t
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
Flag Outputs = PFx, FL0, FL1, FL2, FO.
IFS
IFH
FOH
FOD
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High
Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
OUTPUTS
CLKOUT
FLAG
IRQx
PFx
FI
5
5
t
t
FOH
FOD
1, 2, 3, 4
1, 2, 3, 4
t
IFH
t
IFS
Min
0.25t
0.25t
0.5t
CK
CK
CK
– 5
+ 10
Max
0.5t
CK
+ 4
Unit
ns
ns
ns
ns

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