ADSP-2173BST-80 Analog Devices Inc, ADSP-2173BST-80 Datasheet - Page 28

• Manufacturer Part Number: ADSP-2173BST-80
• Description: IC DSP CONTROLLER 16BIT 128TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2173BST-80

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 20MHz
• Non-volatile Memory: External
• On-chip Ram: 10kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 10KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Host Interface Port
Multiplexed Data and Address (HMD1 = 1)
Read Strobe and Write Strobe (HMD0 = 1)
Timing Requirement:
t
t
t
t
t
t
t
t
t
Switching Characteristic:
t
t
t
t
t
t
NOTES
1
2
3
Start of Write or Read = HDS Low and HSEL Low.
End of Write or Read = HDS High and HSEL High.
Read or Write Pulse Width = HDS Low and HSEL Low.
HALP
HASU
HAH
HALS
HSU
HDSU
HWDH
HH
HRWP
HSHK
HKH
HDE
HDD
HRDH
HRDD
Host Write Cycle
Host Read Cycle
ALE Pulse Width
HAD15–0 Address Setup before ALE Low
HAD15–0 Address Hold after ALE Low
Start of Write or Read after ALE Low
HRW Setup before Start of Write or Read
HAD15–0 Data Setup before End of Write
HAD15–0 Data Hold after End of Write
HRW Hold after End of Write or Read
Read or Write Pulse Width
HACK Low after Start of Write or Read
HACK Hold after End of Write or Read
HAD15–0 Data Enabled after Start of Read
HAD15–0 Data Valid after Start of Read
HAD15–0 Data Hold after End of Read
HAD15–0 Data Disabled after End of Read
HD15–0
HD15–0
HACK
HACK
HSEL
HRW
HSEL
HRW
HDS
HDS
ALE
ALE
Figure 17. Host Interface Port (HMD1 = 1, HMD0 = 1)
t
t
t
t
HALP
HASU
HASU
HALP
ADDRESS
ADDRESS
3
t
t
HAH
HAH
t
HALS
t
HALS
1
2
2
1
2
2
1
t
1
HSU
2
2
1
–28–
t
HDE
t
t
HDD
HSU
t
t
HSHK
HSHK
t
t
HRWP
HRWP
t
HDSU
DATA
Min
10
5
2
10
5
5
3
3
20
0
0
0
0
DATA
t
HRDH
t
t
t
HWDH
t
HKH
t
HKH
HH
HH
t
HRDD
Max
15
15
18
7
REV. A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns