ADSP-2173BST-80 Analog Devices Inc, ADSP-2173BST-80 Datasheet - Page 9

• Manufacturer Part Number: ADSP-2173BST-80
• Description: IC DSP CONTROLLER 16BIT 128TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2173BST-80

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 20MHz
• Non-volatile Memory: External
• On-chip Ram: 10kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 10KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

REV. A
Stand-Alone ROM Execution
When the MMAP and BMODE pins both are set to 1, the
ROM is automatically enabled and execution commences from
program memory location 0x0800 at the start of ROM. This
feature lets an embedded design operate without external
memory components. To operate in this mode, the ROM coded
program must copy an interrupt vector table to the appropriate
locations in program memory RAM. In this mode, the ROM
enable bit defaults to 1 during reset.
MMAP = 0 Boot from EPROM,
MMAP = 1 No booting, execution
Ordering Procedure for ADSP-2172 Processors
To place an order for a custom ROM-coded ADSP-2172 pro-
cessor, you must:
1. Complete the following forms contained in the ADSP ROM
2. Return the forms to Analog Devices along with two copies of
3. Place a purchase order with Analog Devices for nonrecurring
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks are
identical, and recalculates the checksums for the .EXE file en-
tered into the ROM Manager System. The checksum data, in the
form of a ROM memory map, a hard copy of the .EXE file, and a
ROM Data Verification Form are returned to you for inspection.
A signed ROM Verification Form and a purchase order for pro-
duction units are required prior to any product being manufac-
tured. Prototype units may be applied toward the minimum
order quantity.
Ordering Package, available from your Analog Devices sales
representative:
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-production ROM Products.
the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
IBM PC (DOS 2.01 or higher).
engineering charges (NRE) associated with ROM product
development.
ADSP-2172 ROM Specification Form
BMODE = 0
then execution starts
at internal RAM
location 0x0000
starts at external memory execution starts at
location 0x0000
Table III. Boot Summary Table
BMODE = 1
Boot from HIP, then
execution starts at
internal RAM location
0x0000
Stand-Alone Mode,
internal ROM location
0x0800
–9–
Upon completion of the prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for pro-
duction units. An invoice against your purchase order for the
NRE charges is issued at this time.
There is a charge for each ROM mask generated and a mini-
mum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
Data Memory Interface
The data memory address (DMA) bus is 14 bits wide. The bidi-
rectional external data bus is 24 bits wide, with the upper 16
bits (D8–D23) used for data memory data (DMD) transfers.
The data memory select (DMS) signal indicates access to the
data memory and can be used as a chip select signal. The write
(WR) signal indicates a write operation and can be used as a
write strobe. The read (RD) signal indicates a read operation
and can be used as a read strobe or output enable signal.
The ADSP-217x supports memory-mapped I/O, with the pe-
ripherals memory mapped into the data or program memory ad-
dress spaces and accessed by the processor in the same manner.
Data Memory Map
The on-chip data memory RAM resides in the 2K words of data
memory beginning at address 0x3000, as shown in Figure 6. In
addition, data memory locations from 0x3800 to the end of data
memory at 0x3FFF are reserved. Control registers for the sys-
tem, timer, wait state configuration, host interface port, and se-
rial port operations are located in this region of memory.
The remaining 12K of data memory is external. External data
memory is divided into three zones, each associated with its own
wait state generator. By mapping peripherals into different
zones, you can accommodate peripherals with different wait
state requirements. All zones default to 7 wait states after
RESET. For compatibility with other ADSP-2100 Family pro-
cessors, bit definitions for DWAIT 3 and DWAIT4 are shown
in the Data Memory Wait State Control Register, but they are
not used by the ADSP-217x.
ADSP-2171/ADSP-2172/ADSP-2173
MEMORY MAPPED
DATA MEMORY
Figure 6. ADSP-217x Data Memory Map
REGISTERS/
RESERVED
EXTERNAL
DATA RAM
RESERVED
INTERNAL
12K
2K
1K
3FFF
2FFF
3000
3BFF
3C00
0000
37FF
3800
(10K EXTERNAL)
(1K EXTERNAL)
(1K EXTERNAL)
WAIT STATES
NO WAIT
STATES
DWAIT 0
DWAIT 1
DWAIT 2
0000
03FF
0400
07FF
0800
2FFF
3000
3FFF