EP1C6T144I7N Altera, EP1C6T144I7N Datasheet - Page 86

• Manufacturer Part Number: EP1C6T144I7N
• Description: IC CYCLONE FPGA 5980 LE 144-TQFP
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C6T144I7N

• Number Of Logic Elements/cells: 5980
• Number Of Labs/clbs: 598
• Total Ram Bits: 92160
• Number Of I /o: 98
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 5980
• # I/os (max): 98
• Frequency (max): 320.1MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 5980
• Ram Bits: 92160
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1818; EP1C6T144I7N

Cyclone Device Handbook, Volume 1
4–16
Preliminary
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I N S U
I N H
O U T C O
I N S U P L L
I N H P L L
Table 4–29. Cyclone Global Clock External I/O Timing Parameters
Symbol
Setup time for input or bidirectional pin using IOE input
register with global clock fed by
Hold time for input or bidirectional pin using IOE input
register with global clock fed by
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock fed by
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
Figure 4–2. External Timing in Cyclone Devices
All external I/O timing parameters shown are for 3.3-V LVTTL I/O
standard with the maximum current strength and fast slew rate. For
external I/O timing using standards other than LVTTL or for different
current strengths, use the I/O standard input and output delay adders in
Tables 4–40
Table 4–29
clock networks.
Dedicated
Clock
Parameter
shows the external I/O timing parameters when using global
through 4–44.
CLK
CLK
pin
pin
CLK
pin
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
PRN
PRN
Q
Q
Q
Notes
C
LOAD
(1),
(2)
= 10 pF
(Part 1 of 2)
Conditions
Altera Corporation
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—
—
—
—
XZ
ZX
INSU
INH
OUTCO
Bidirectional
Pin
May 2008