EP2S60F484C5N Altera, EP2S60F484C5N Datasheet - Page 132

• Manufacturer Part Number: EP2S60F484C5N
• Description: IC STRATIX II FPGA 60K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F484C5N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 334
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 334
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1908; EP2S60F484C5N

Stratix II Hot-Socketing Specifications
4–2
Stratix II Device Handbook, Volume 1
Devices Can Be Driven Before Power-Up
You can drive signals into the I/O pins, dedicated input pins and
dedicated clock pins of Stratix II devices before or during power-up or
power-down without damaging the device. Stratix II devices support any
power-up or power-down sequence (V
to simplify system level design.
I/O Pins Remain Tri-Stated During Power-Up
A device that does not support hot-socketing may interrupt system
operation or cause contention by driving out before or during power-up.
In a hot socketing situation, Stratix II device's output buffers are turned
off during system power-up or power-down. Stratix II device also does
not drive out until the device is configured and has attained proper
operating conditions.
Signal Pins Do Not Drive the V
Supplies
Devices that do not support hot-socketing can short power supplies
together when powered-up through the device signal pins. This irregular
power-up can damage both the driving and driven devices and can
disrupt card power-up.
Stratix II devices do not have a current path from I/O pins, dedicated
input pins, or dedicated clock pins to the V
before or during power-up. A Stratix II device may be inserted into (or
removed from) a powered-up system board without damaging or
interfering with system-board operation. When hot-socketing, Stratix II
devices may have a minimal effect on the signal integrity of the
backplane.
1
■
■
The hot socketing DC specification is: | I
The hot socketing AC specification is: | I
less.
You can power up or power down the V
pins in any sequence. The power supply ramp rates can range
from 100 μs to 100 ms. All V
within 100 ms of each other to prevent I/O pins from driving
out. During hot socketing, the I/O pin capacitance is less than 15
pF and the clock pin capacitance is less than 20 pF. Stratix II
devices meet the following hot socketing specification.
CCIO
CC
, V
CCIO
supplies must power down
CCINT
, V
CCIO
IOPIN
IOPIN
CCINT
or V
, V
CCIO
CCINT
, and V
| < 300 μA.
| < 8 mA for 10 ns or
CCPD
, V
Altera Corporation
, or V
CCINT
Power
CCPD
CCPD
, and V
) in order
May 2007
pins
CCPD