EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 8

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

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Clock Networks and PLLs
Stratix III Device Handbook, Volume 1
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Stratix III devices have up to 112 DSP blocks. The architectural highlights of the
Stratix III DSP block are the following:
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DSP block multipliers can optionally feed an adder/subtractor or accumulator in the
block depending on user configuration. This option saves ALM routing resources and
increases performance, because all connections and blocks are inside the DSP block.
Additionally, the DSP Block input registers can efficiently implement shift registers
for FIR filter applications, and the Stratix III DSP blocks support rounding and
saturation. The Quartus II software includes megafunctions that control the mode of
operation of the DSP blocks based on user parameter settings.
For more information, refer to the
Stratix III devices provide dedicated Global Clock Networks (GCLKs), Regional Clock
Networks (RCLKs), and Periphery Clock Networks (PCLKs). These clocks are
organized into a hierarchical clock structure that provides up to 104 unique clock
domains (16 GCLK + 88 RCLK) within the Stratix III device and allows for up to 38 (16
GCLK + 22 RCLK) unique GCLK/RCLK clock sources per device quadrant.
Stratix III devices deliver abundant PLL resources with up to 12 PLLs per device and
up to 10 outputs per PLL. Every output can be independently programmed, creating a
unique, customizable clock frequency. Inherent jitter filtration and fine granularity
control over multiply, divide ratios, and dynamic phase-shift reconfiguration provide
the high-performance precision required in today’s high-speed applications. Stratix III
PLLs are feature rich, supporting advanced capabilities such as clock switchover,
reconfigurable phase shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs
can be used for general-purpose clock management supporting multiplication, phase
shifting, and programmable duty cycle. Stratix III PLLs also support external
feedback mode, spread-spectrum input clock tracking, and post-scale counter
cascading.
High-performance, power optimized, fully pipelined multiplication operations
Native support for 9-bit, 12-bit, 18-bit, and 36-bit word lengths
Native support for 18-bit complex multiplications
Efficient support for floating point arithmetic formats (24-bit for Single Precision
and 53-bit for Double Precision)
Signed and unsigned input support
Built-in addition, subtraction, and accumulation units to efficiently combine
multiplication results
Cascading 18-bit input bus to form tap-delay lines
Cascading 44-bit output bus to propagate output results from one block to the next
block
Rich and flexible arithmetic rounding and saturation units
Efficient barrel shifter support
Loopback capability to support adaptive filtering
DSP Blocks in Stratix III Devices
Chapter 1: Stratix III Device Family Overview
© March 2010 Altera Corporation
chapter.
Architecture Features