EP1K100FC256-2 Altera, EP1K100FC256-2 Datasheet - Page 2

• Manufacturer Part Number: EP1K100FC256-2
• Description: IC ACEX 1K FPGA 100K 256-FBGA
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K100FC256-2

• Number Of Logic Elements/cells: 4992
• Number Of Labs/clbs: 624
• Total Ram Bits: 49152
• Number Of I /o: 186
• Number Of Gates: 257000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-FBGA
• Family Name: ACEX™ 1K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4992
• # I/os (max): 186
• Frequency (max): 250MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 4992
• Ram Bits: 49152
• Device System Gates: 257000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1023

ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
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Flexible interconnect
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Powerful I/O pins
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-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2 for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
Operate with a 2.5-V internal supply voltage
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
ClockLock
clock skew, and clock multiplication
Built-in, low-skew clock distribution trees
100% functional testing of all devices; test vectors or scan chains
are not required
Pull-up on I/O pins before and during configuration
FastTrack
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
Clamp to V
Supports hot-socketing
®
TM
Interconnect continuous routing structure for fast,
CCIO
and ClockBoost
user-selectable on a pin-by-pin basis
TM
options for reduced clock delay,
Altera Corporation