EP2SGX30DF780C5N Altera, EP2SGX30DF780C5N Datasheet - Page 94

• Manufacturer Part Number: EP2SGX30DF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30DF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1754

Digital Signal Processing (DSP) Block
Figure 2–59. DSP Block Interconnect Interface
2–86
Stratix II GX Device Handbook, Volume 1
Link Interconnects
R4, C4 & Direct
The DSP block is divided into four block units that interface with four
LAB rows on the left and right. Each block unit can be considered one
complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local
interconnect region is associated with each DSP block. Like a LAB, this
interconnect region can be fed with 16 direct link interconnects from the
LAB to the left or right of the DSP block in the same row. R4 and C4
routing resources can access the DSP block’s local interconnect region.
The outputs also work similarly to LAB outputs. Eighteen outputs from
the DSP block can drive to the left LAB through direct link interconnects
and 18 can drive to the right LAB through direct link interconnects. All 36
outputs can drive to R4 and C4 routing interconnects. Outputs can drive
right- or left-column routing.
Figures 2–59
and
2–60
A2[17..0]
B2[17..0]
A3[17..0]
B3[17..0]
A4[17..0]
B4[17..0]
A1[17..0]
B1[17..0]
DSP Block
OG[17..0]
OC[17..0]
OD[17..0]
OH[17..0]
OA[17..0]
OB[17..0]
OE[17..0]
OF[17..0]
show the DSP block interfaces to LAB rows.
R4, C4 & Direct
Link Interconnects
Altera Corporation
October 2007