EP2SGX30CF780C4N Altera, EP2SGX30CF780C4N Datasheet - Page 11

• Manufacturer Part Number: EP2SGX30CF780C4N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30CF780C4N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1927; EP2SGX30CF780C4N

Altera Corporation
October 2007
Figure 2–2. Elements of the Transceiver Block
Each Stratix II GX transceiver channel consists of a transmitter and
receiver. The transceivers are grouped in four and share PLL resources.
Each transmitter has access to one of two PLLs. The transmitter contains
the following:
■
■
■
■
■
The receiver contains the following:
■
■
■
■
■
■
■
■
■
■
■
■
Designers can preset Stratix II GX transceiver functions using the
Quartus
differential output voltage (V
Stratix II GX transceiver channel supports various loopback modes and is
Transmitter phase compensation first-in first-out (FIFO) buffer
Byte serializer (optional)
8B/10B encoder (optional)
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
Receiver differential input buffer
Receiver lock detector and run length checker
Clock recovery unit (CRU)
Deserializer
Pattern detector
Word aligner
Lane deskew
Rate matcher (optional)
8B/10B decoder (optional)
Byte deserializer (optional)
Byte ordering
Receiver phase compensation FIFO buffer
®
II software. In addition, pre-emphasis, equalization, and
Stratix II GX
Logic Array
Transceiver Block
(PLLs, State Machines,
OD
Supporting Blocks
Programming)
) are dynamically programmable. Each
Channel 1
Channel 0
Channel 2
Channel 3
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
RX1
TX1
RX0
TX0
REFCLK_1
REFCLK_0
RX2
TX2
RX3
TX3
2–3