EP2S60F672C3N Altera, EP2S60F672C3N Datasheet - Page 51

• Manufacturer Part Number: EP2S60F672C3N
• Description: IC STRATIX II FPGA 60K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F672C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 492
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 492
• Frequency (max): 816.99MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1912; EP2S60F672C3N

Figure 2–28. DSP Block Diagram for 18 × 18-Bit Configuration
Altera Corporation
May 2007
Optional Serial Shift
Register Outputs to
interface block
Next DSP Block
in the Column
From the row
Register Inputs from
Optional Serial Shift
Previous DSP Block
PRN
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
PRN
PRN
PRN
PRN
PRN
PRN
PRN
Q
Q
Q
Q
Q
Q
Q
Q
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
Saturate
Saturate
Saturate
Saturate
Round/
Round/
Round/
Round/
Q1.15
Q1.15
Q1.15
Q1.15
Multiplier Block
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
PRN
PRN
PRN
PRN
Q
Q
Q
Q
Adder Output Block
Optional Pipline
Register Stage
Accumulator
Accumulator
Optional Stage Configurable
as Accumulator or Dynamic
Subtractor/
Subtractor/
Adder/
Adder/
2
1
Adder/Subtractor
Stratix II Device Handbook, Volume 1
Saturate
Saturate
Multipliers Together
Round/
Round/
Q1.15
Q1.15
Summation Stage
for Adding Four
Summation
Block
Adder
Interconnect
to MultiTrack
Multiplexer
Selection
Output
Stratix II Architecture
ENA
D
CLRN
Q
2–43