EP1S25F780C5 Altera, EP1S25F780C5 Datasheet - Page 37

• Manufacturer Part Number: EP1S25F780C5
• Description: IC STRATIX FPGA 25K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S25F780C5

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 597
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 597
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1120

Altera Corporation
July 2005
In addition to true dual-port memory, the memory blocks support simple
dual-port and single-port RAM. Simple dual-port memory supports a
simultaneous read and write and can either read old data before the write
occurs or just read the don’t care bits. Single-port memory supports non-
simultaneous reads and writes, but the q[] port will output the data once
it has been written to the memory (if the outputs are not registered) or
after the next rising edge of the clock (if the outputs are registered). For
more information, see
Stratix & Stratix GX Devices
Figure 2–13
TriMatrix memory.
Figure 2–13. Simple Dual-Port & Single-Port Memory Configurations
Note to
(1)
The memory blocks also enable mixed-width data ports for reading and
writing to the RAM ports in dual-port RAM configuration. For example,
the memory block can be written in ×1 mode at port A and read out in ×16
mode from port B.
Two single-port memory blocks can be implemented in a single M4K block as long
as each of the two independent block sizes is equal to or less than half of the M4K
block size.
Figure
Simple Dual-Port Memory
Single-Port Memory (1)
shows these different RAM memory port configurations for
2–13:
data[ ]
wraddress[ ]
wren
inclocken
inaclr
data[ ]
address[ ]
wren
inclocken
inaclr
inclock
inclock
Chapter 2, TriMatrix Embedded Memory Blocks in
of the
Stratix Device Handbook, Volume
Stratix Device Handbook, Volume 1
rdaddress[ ]
outclocken
outclocken
outclock
outclock
outaclr
outaclr
rden
q[ ]
q[ ]
Stratix Architecture
2.
2–23